Add MX25 support to nand_spl fsl nfc driver

MX25 has a different version of the fsl_nfc
flash controller known as version 1.1.

Add support to the nand_spl fsl_nfc driver

Versioning differs from mainline mxc kernel driver
no consensus yet on if the naming here and in
Redboot or the kernel is "correct".

Signed-off-by: John Rigby <jcrigby@gmail.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
CC: Scott Wood <scottwood@freescale.com>

include/fsl_nfc.h

@@ -1,5 +1,4 @@
 /*
- *
  * (c) 2009 Magnus Lilja <lilja.magnus@gmail.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -25,21 +24,57 @@
 #define __FSL_NFC_H
 
 /*
+ * TODO: Use same register defs for nand_spl mxc nand driver
+ * and mtd mxc nand driver.
+ *
  * Register map and bit definitions for the Freescale NAND Flash
- * Controller present in i.MX31 and other devices.
+ * Controller present in various i.MX devices.
+ *
+ * MX31 and MX27 have version 1 which has
+ * 	4 512 byte main buffers and
+ * 	4 16 byte spare buffers
+ * 	to support up to 2K byte pagesize nand.
+ * 	Reading or writing a 2K page requires 4 FDI/FDO cycles.
+ *
+ * MX25 has version 1.1 which has
+ * 	8 512 byte main buffers and
+ * 	8 64 byte spare buffers
+ * 	to support up to 4K byte pagesize nand.
+ * 	Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
+ *      Also some of registers are moved and/or changed meaning as seen below.
  */
+#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
+#define MXC_NFC_V1
+#elif defined(CONFIG_MX25)
+#define MXC_NFC_V1_1
+#else
+#warning "MXC NFC version not defined"
+#endif
+
+#if defined(MXC_NFC_V1)
+#define NAND_MXC_NR_BUFS		4
+#define NAND_MXC_SPARE_BUF_SIZE		16
+#define NAND_MXC_REG_OFFSET		0xe00
+#define NAND_MXC_2K_MULTI_CYCLE		1
+#elif defined(MXC_NFC_V1_1)
+#define NAND_MXC_NR_BUFS		8
+#define NAND_MXC_SPARE_BUF_SIZE		64
+#define NAND_MXC_REG_OFFSET		0x1e00
+#else
+#error "define CONFIG_NAND_MXC_VXXX to use the mxc spl_nand driver"
+#endif
 
 struct fsl_nfc_regs {
-	u32 main_area0[128]; /* @0x000 */
-	u32 main_area1[128];
-	u32 main_area2[128];
-	u32 main_area3[128];
-	u32 spare_area0[4];
-	u32 spare_area1[4];
-	u32 spare_area2[4];
-	u32 spare_area3[4];
-	u32 reserved1[64 - 16 + 64 * 5];
-	u16 bufsiz; /* @ 0xe00 */
+	u32 main_area[NAND_MXC_NR_BUFS][512/4];
+	u32 spare_area[NAND_MXC_NR_BUFS][NAND_MXC_SPARE_BUF_SIZE/4];
+	/*
+	 * reserved size is offset of nfc registers
+	 * minus total main and spare sizes
+	 */
+	u8 reserved1[NAND_MXC_REG_OFFSET
+		- NAND_MXC_NR_BUFS * (512 + NAND_MXC_SPARE_BUF_SIZE)];
+#if defined(MXC_NFC_V1)
+	u16 bufsiz;
 	u16 reserved2;
 	u16 buffer_address;
 	u16 flash_add;
@@ -54,6 +89,30 @@ struct fsl_nfc_regs {
 	u16 nand_flash_wr_pr_st;
 	u16 nand_flash_config1;
 	u16 nand_flash_config2;
+#elif defined(MXC_NFC_V1_1)
+	u16 reserved2[2];
+	u16 buffer_address;
+	u16 flash_add;
+	u16 flash_cmd;
+	u16 configuration;
+	u16 ecc_status_result;
+	u16 ecc_status_result2;
+	u16 spare_area_size;
+	u16 nf_wr_prot;
+	u16 reserved3[2];
+	u16 nand_flash_wr_pr_st;
+	u16 nand_flash_config1;
+	u16 nand_flash_config2;
+	u16 reserved4;
+	u16 unlock_start_blk_add0;
+	u16 unlock_end_blk_add0;
+	u16 unlock_start_blk_add1;
+	u16 unlock_end_blk_add1;
+	u16 unlock_start_blk_add2;
+	u16 unlock_end_blk_add2;
+	u16 unlock_start_blk_add3;
+	u16 unlock_end_blk_add3;
+#endif
 };
 
 /*
@@ -98,6 +157,9 @@ struct fsl_nfc_regs {
  */
 #define NFC_INT		0x8000
 
+#ifdef MXC_NFC_V1_1
+#define NFC_4_8N_ECC	(1 << 0)
+#endif
 #define NFC_SP_EN	(1 << 2)
 #define NFC_ECC_EN	(1 << 3)
 #define NFC_INT_MSK	(1 << 4)

nand_spl/nand_boot_fsl_nfc.c

@@ -26,11 +26,15 @@
 
 #include <common.h>
 #include <nand.h>
+#ifdef CONFIG_MX31
 #include <asm-arm/arch/mx31-regs.h>
+#else
+#include <asm-arm/arch/imx-regs.h>
+#endif
 #include <asm/io.h>
 #include <fsl_nfc.h>
 
-static struct fsl_nfc_regs *nfc;
+struct fsl_nfc_regs *nfc;
 
 static void nfc_wait_ready(void)
 {
@@ -45,13 +49,35 @@ static void nfc_wait_ready(void)
 	writew(tmp, &nfc->nand_flash_config2);
 }
 
-static void nfc_nand_init(void)
+void nfc_nand_init(void)
 {
+#if defined(MXC_NFC_V1_1)
+	int ecc_per_page  = CONFIG_SYS_NAND_PAGE_SIZE / 512;
+	int config1;
+
+	writew(CONFIG_SYS_NAND_SPARE_SIZE / 2, &nfc->spare_area_size);
+
+	/* unlocking RAM Buff */
+	writew(0x2, &nfc->configuration);
+
+	/* hardware ECC checking and correct */
+	config1 = readw(&nfc->nand_flash_config1) | NFC_ECC_EN | 0x800;
+	/*
+	 * if spare size is larger that 16 bytes per 512 byte hunk
+	 * then use 8 symbol correction instead of 4
+	 */
+	if ((CONFIG_SYS_NAND_SPARE_SIZE / ecc_per_page) > 16)
+		config1 &= ~NFC_4_8N_ECC;
+	else
+		config1 |= NFC_4_8N_ECC;
+	writew(config1, &nfc->nand_flash_config1);
+#elif defined(MXC_NFC_V1)
 	/* unlocking RAM Buff */
 	writew(0x2, &nfc->configuration);
 
 	/* hardware ECC checking and correct */
 	writew(NFC_ECC_EN, &nfc->nand_flash_config1);
+#endif
 }
 
 static void nfc_nand_command(unsigned short command)
@@ -65,12 +91,12 @@ static void nfc_nand_page_address(unsigned int page_address)
 {
 	unsigned int page_count;
 
-	writew(0x00, &nfc->flash_cmd);
+	writew(0x00, &nfc->flash_add);
 	writew(NFC_ADDR, &nfc->nand_flash_config2);
 	nfc_wait_ready();
 
-	/* code only for 2kb flash */
-	if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) {
+	/* code only for large page flash */
+	if (CONFIG_SYS_NAND_PAGE_SIZE > 512) {
 		writew(0x00, &nfc->flash_add);
 		writew(NFC_ADDR, &nfc->nand_flash_config2);
 		nfc_wait_ready();
@@ -88,22 +114,38 @@ static void nfc_nand_page_address(unsigned int page_address)
 			page_count = page_count >> 8;
 		} while (page_count);
 	}
+
+	writew(0x00, &nfc->flash_add);
+	writew(NFC_ADDR, &nfc->nand_flash_config2);
+	nfc_wait_ready();
 }
 
 static void nfc_nand_data_output(void)
 {
+	int config1 = readw(&nfc->nand_flash_config1);
+#ifdef NAND_MXC_2K_MULTI_CYCLE
 	int i;
+#endif
 
+	config1 |= NFC_ECC_EN | NFC_INT_MSK;
+	writew(config1, &nfc->nand_flash_config1);
+	writew(0, &nfc->buffer_address);
+	writew(NFC_OUTPUT, &nfc->nand_flash_config2);
+	nfc_wait_ready();
+#ifdef NAND_MXC_2K_MULTI_CYCLE
 	/*
-	 * The NAND controller requires four output commands for
-	 * large page devices.
+	 * This NAND controller requires multiple input commands
+	 * for pages larger than 512 bytes.
 	 */
-	for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
-		writew(NFC_ECC_EN, &nfc->nand_flash_config1);
-		writew(i, &nfc->buffer_address); /* read in i:th buffer */
+	for (i = 1; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) {
+		config1 = readw(&nfc->nand_flash_config1);
+		config1 |= NFC_ECC_EN | NFC_INT_MSK;
+		writew(config1, &nfc->nand_flash_config1);
+		writew(i, &nfc->buffer_address);
 		writew(NFC_OUTPUT, &nfc->nand_flash_config2);
 		nfc_wait_ready();
 	}
+#endif
 }
 
 static int nfc_nand_check_ecc(void)
@@ -121,7 +163,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf)
 	nfc_nand_command(NAND_CMD_READ0);
 	nfc_nand_page_address(page_address);
 
-	if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
+	if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
 		nfc_nand_command(NAND_CMD_READSTART);
 
 	nfc_nand_data_output(); /* fill the main buffer 0 */
@@ -129,7 +171,7 @@ static int nfc_read_page(unsigned int page_address, unsigned char *buf)
 	if (nfc_nand_check_ecc())
 		return -1;
 
-	src = &nfc->main_area0[0];
+	src = &nfc->main_area[0][0];
 	dst = (u32 *)buf;
 
 	/* main copy loop from NAND-buffer to SDRAM memory */
@@ -154,12 +196,12 @@ static int is_badblock(int pagenumber)
 		nfc_nand_command(NAND_CMD_READ0);
 		nfc_nand_page_address(page);
 
-		if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800)
+		if (CONFIG_SYS_NAND_PAGE_SIZE > 512)
 			nfc_nand_command(NAND_CMD_READSTART);
 
 		nfc_nand_data_output(); /* fill the main buffer 0 */
 
-		src = &nfc->spare_area0[0];
+		src = &nfc->spare_area[0][0];
 
 		/*
 		 * IMPORTANT NOTE: The nand flash controller uses a non-
@@ -209,7 +251,7 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf)
 		if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) {
 			/*
 			 * Yes, new block. See if this block is good. If not,
-			 * loop until we find i good block.
+			 * loop until we find a good block.
 			 */
 			while (is_badblock(page)) {
 				page = page + CONFIG_SYS_NAND_PAGE_COUNT;