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rockchip: rk322x: fix pd_bus hclk/pclk

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The pd_bus hclk/pclk source is pd_bus aclk, not the PLL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
master
Kever Yang 7 years ago committed by Philipp Tomsich
parent 5d62aba4e3
commit f3f6591ca3
1 changed files with 3 additions and 3 deletions
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  1. 6
      drivers/clk/rockchip/clk_rk322x.c

6
drivers/clk/rockchip/clk_rk322x.c
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@ -117,16 +117,16 @@ static void rkclk_init(struct rk322x_cru *cru)
pclk_div << CORE_PERI_DIV_SHIFT);
/*
* select apll as pd_bus bus clock source and
* select gpll as pd_bus bus clock source and
* set up dependent divisors for PCLK/HCLK and ACLK clocks.
*/
aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
pclk_div = GPLL_HZ / BUS_PCLK_HZ - 1;
pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
assert((pclk_div + 1) * BUS_PCLK_HZ == GPLL_HZ && pclk_div <= 0x7);
hclk_div = GPLL_HZ / BUS_HCLK_HZ - 1;
hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
assert((hclk_div + 1) * BUS_HCLK_HZ == GPLL_HZ && hclk_div <= 0x3);
rk_clrsetreg(&cru->cru_clksel_con[0],

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