arm: v7: Kconfig: Introduce SYS_ARM_CACHE_CP15

Certain ARM architectures like ARMv7-A, ARMv7-R has support for
enabling caches using CP15 registers. To have a common support
for all these architectures, introduce a Kconfig symbol
SYS_ARM_CACHE_CP15 that selects cache-cp15.c

Tested-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

arch/arm/Kconfig

@@ -74,8 +74,15 @@ config ARM_ASM_UNIFIED
 config THUMB2_KERNEL
 	bool
 
+config SYS_ARM_CACHE_CP15
+	bool "CP15 based cache enabling support"
+	help
+	  Select this if your processor suports enabling caches by using
+	  CP15 registers.
+
 config SYS_ARM_MMU
 	bool "MMU-based Paged Memory Management Support"
+	select SYS_ARM_CACHE_CP15
 	help
 	  Select if you want MMU-based virtualised addressing space
 	  support by paged memory management.

arch/arm/lib/Makefile

@@ -61,11 +61,7 @@ obj-y	+= reset.o
 endif
 
 obj-y	+= cache.o
-ifndef CONFIG_ARM64
-ifndef CONFIG_CPU_V7M
-obj-y	+= cache-cp15.o
-endif
-endif
+obj-$(CONFIG_SYS_ARM_CACHE_CP15)	+= cache-cp15.o
 
 obj-y	+= psci-dt.o