T1040RDB, T1042RDB header files are very similar so merged into new header file T104xRDB. T104xRDB header file can support both T1040RDB and T1042RDB_PI header. Patch makes following changes -Update Boards.cfg file for T1040RDB and T1042RDB_PI -Add new T104xRDB header file -Delete T1040RDB, T1042RDB_PI header file Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>master
vijay rai
11 years ago
committed by
York Sun
parent
613ab32c47
commit
f4c3917a3c
@ -1,695 +0,0 @@ |
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/*
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#ifndef __CONFIG_H |
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#define __CONFIG_H |
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/*
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* T1042RDB_PI board configuration file |
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*/ |
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#define CONFIG_T104xRDB |
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#define CONFIG_T1042RDB_PI |
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#define CONFIG_PHYS_64BIT |
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#ifdef CONFIG_RAMBOOT_PBL |
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#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE |
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc |
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#endif |
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|
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/* High Level Configuration Options */ |
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#define CONFIG_BOOKE |
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#define CONFIG_E500 /* BOOKE e500 family */ |
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#define CONFIG_E500MC /* BOOKE e500mc family */ |
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#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ |
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#define CONFIG_MP /* support multiple processors */ |
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#ifndef CONFIG_SYS_TEXT_BASE |
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#define CONFIG_SYS_TEXT_BASE 0xeff40000 |
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#endif |
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#ifndef CONFIG_RESET_VECTOR_ADDRESS |
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc |
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#endif |
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#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
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#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS |
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#define CONFIG_FSL_IFC /* Enable IFC Support */ |
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#define CONFIG_PCI /* Enable PCI/PCIE */ |
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#define CONFIG_PCI_INDIRECT_BRIDGE |
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#define CONFIG_PCIE1 /* PCIE controler 1 */ |
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#define CONFIG_PCIE2 /* PCIE controler 2 */ |
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#define CONFIG_PCIE3 /* PCIE controler 3 */ |
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#define CONFIG_PCIE4 /* PCIE controler 4 */ |
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#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
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#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ |
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#define CONFIG_FSL_LAW /* Use common FSL init code */ |
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#define CONFIG_ENV_OVERWRITE |
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#ifdef CONFIG_SYS_NO_FLASH |
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#define CONFIG_ENV_IS_NOWHERE |
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#else |
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#define CONFIG_FLASH_CFI_DRIVER |
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#define CONFIG_SYS_FLASH_CFI |
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
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#endif |
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#ifndef CONFIG_SYS_NO_FLASH |
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#if defined(CONFIG_SPIFLASH) |
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#define CONFIG_SYS_EXTRA_ENV_RELOC |
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#define CONFIG_ENV_IS_IN_SPI_FLASH |
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ |
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#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ |
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#define CONFIG_ENV_SECT_SIZE 0x10000 |
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#elif defined(CONFIG_SDCARD) |
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#define CONFIG_SYS_EXTRA_ENV_RELOC |
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#define CONFIG_ENV_IS_IN_MMC |
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#define CONFIG_SYS_MMC_ENV_DEV 0 |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_ENV_OFFSET (512 * 1658) |
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#elif defined(CONFIG_NAND) |
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#define CONFIG_SYS_EXTRA_ENV_RELOC |
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#define CONFIG_ENV_IS_IN_NAND |
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#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
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#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) |
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#else |
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#define CONFIG_ENV_IS_IN_FLASH |
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
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#endif |
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#else /* CONFIG_SYS_NO_FLASH */ |
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#define CONFIG_ENV_SIZE 0x2000 |
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ |
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#endif |
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#define CONFIG_SYS_CLK_FREQ 100000000 |
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#define CONFIG_DDR_CLK_FREQ 66666666 |
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/*
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* These can be toggled for performance analysis, otherwise use default. |
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*/ |
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#define CONFIG_SYS_CACHE_STASHING |
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#define CONFIG_BACKSIDE_L2_CACHE |
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#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E |
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#define CONFIG_BTB /* toggle branch predition */ |
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#define CONFIG_DDR_ECC |
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#ifdef CONFIG_DDR_ECC |
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef |
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#endif |
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#define CONFIG_ENABLE_36BIT_PHYS |
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#define CONFIG_ADDR_MAP |
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#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ |
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#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
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#define CONFIG_SYS_MEMTEST_END 0x00400000 |
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#define CONFIG_SYS_ALT_MEMTEST |
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#define CONFIG_PANIC_HANG /* do not reset board on panic */ |
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/*
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* Config the L3 Cache as L3 SRAM |
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*/ |
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#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 |
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#define CONFIG_SYS_DCSRBAR 0xf0000000 |
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#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull |
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/*
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* DDR Setup |
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*/ |
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#define CONFIG_VERY_BIG_RAM |
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE |
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/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ |
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
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#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) |
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#define CONFIG_DDR_SPD |
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#define CONFIG_SYS_DDR_RAW_TIMING |
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#define CONFIG_SYS_FSL_DDR3 |
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#define CONFIG_SYS_SPD_BUS_NUM 0 |
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#define SPD_EEPROM_ADDRESS 0x51 |
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#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
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/*
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* IFC Definitions |
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*/ |
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#define CONFIG_SYS_FLASH_BASE 0xe8000000 |
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#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) |
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#define CONFIG_SYS_NOR_CSPR_EXT (0xf) |
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#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ |
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V) |
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) |
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/* NOR Flash Timing Params */ |
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#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 |
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ |
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5)) |
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ |
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FTIM1_NOR_TRAD_NOR(0x1A) |\
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FTIM1_NOR_TSEQRAD_NOR(0x13)) |
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ |
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWP(0x1c)) |
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#define CONFIG_SYS_NOR_FTIM3 0x0 |
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#define CONFIG_SYS_FLASH_QUIET_TEST |
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
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#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ |
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ |
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#define CONFIG_SYS_FLASH_EMPTY_INFO |
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#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
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/* CPLD on IFC */ |
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#define CONFIG_SYS_CPLD_BASE 0xffdf0000 |
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#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) |
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#define CONFIG_SYS_CSPR2_EXT (0xf) |
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#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ |
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V) |
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#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) |
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#define CONFIG_SYS_CSOR2 0x0 |
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/* CPLD Timing parameters for IFC CS2 */ |
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#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ |
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e)) |
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#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ |
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FTIM1_GPCM_TRAD(0x1f)) |
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#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ |
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FTIM2_GPCM_TCH(0x0) | \
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FTIM2_GPCM_TWP(0x1f)) |
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#define CONFIG_SYS_CS2_FTIM3 0x0 |
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/* NAND Flash on IFC */ |
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#define CONFIG_NAND_FSL_IFC |
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#define CONFIG_SYS_NAND_BASE 0xff800000 |
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#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) |
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#define CONFIG_SYS_NAND_CSPR_EXT (0xf) |
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V) |
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) |
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
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| CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ |
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#define CONFIG_SYS_NAND_ONFI_DETECTION |
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/* ONFI NAND Flash mode0 Timing Params */ |
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ |
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a)) |
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ |
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18)) |
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ |
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e)) |
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#define CONFIG_SYS_NAND_FTIM3 0x0 |
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#define CONFIG_SYS_NAND_DDR_LAW 11 |
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 |
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#define CONFIG_MTD_NAND_VERIFY_WRITE |
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#define CONFIG_CMD_NAND |
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#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) |
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#if defined(CONFIG_NAND) |
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT |
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK |
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR |
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 |
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 |
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 |
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 |
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT |
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR |
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK |
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR |
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 |
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 |
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 |
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 |
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#else |
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT |
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK |
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR |
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 |
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 |
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 |
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 |
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT |
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR |
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK |
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR |
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#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 |
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#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 |
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#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 |
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#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 |
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#endif |
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
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#if defined(CONFIG_RAMBOOT_PBL) |
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#define CONFIG_SYS_RAMBOOT |
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#endif |
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#define CONFIG_BOARD_EARLY_INIT_R |
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#define CONFIG_MISC_INIT_R |
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#define CONFIG_HWCONFIG |
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/* define to use L1 as initial stack */ |
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#define CONFIG_L1_INIT_RAM |
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#define CONFIG_SYS_INIT_RAM_LOCK |
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#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ |
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf |
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 |
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/* The assembler doesn't like typecast */ |
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#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ |
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((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) |
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#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 |
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
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GENERATED_GBL_DATA_SIZE) |
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) |
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/* Serial Port - controlled on board with jumper J8
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* open - index 2 |
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* shorted - index 1 |
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*/ |
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#define CONFIG_CONS_INDEX 1 |
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#define CONFIG_SYS_NS16550 |
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#define CONFIG_SYS_NS16550_SERIAL |
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#define CONFIG_SYS_NS16550_REG_SIZE 1 |
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) |
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#define CONFIG_SYS_BAUDRATE_TABLE \ |
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} |
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) |
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) |
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#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) |
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#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) |
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#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ |
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
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/* Use the HUSH parser */ |
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#define CONFIG_SYS_HUSH_PARSER |
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
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/* pass open firmware flat tree */ |
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#define CONFIG_OF_LIBFDT |
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#define CONFIG_OF_BOARD_SETUP |
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#define CONFIG_OF_STDOUT_VIA_ALIAS |
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/* new uImage format support */ |
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#define CONFIG_FIT |
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#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ |
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/* I2C */ |
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#define CONFIG_SYS_I2C |
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#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ |
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#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ |
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F |
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#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ |
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#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F |
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 |
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#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 |
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/* I2C bus multiplexer */ |
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#define I2C_MUX_PCA_ADDR 0x70 |
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/*
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* RTC configuration |
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*/ |
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#define RTC |
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#define CONFIG_RTC_DS1337 1 |
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
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/*DVI encoder*/ |
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#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 |
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/*
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* eSPI - Enhanced SPI |
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*/ |
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#define CONFIG_FSL_ESPI |
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#define CONFIG_SPI_FLASH |
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#define CONFIG_SPI_FLASH_STMICRO |
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#define CONFIG_CMD_SF |
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#define CONFIG_SF_DEFAULT_SPEED 10000000 |
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#define CONFIG_SF_DEFAULT_MODE 0 |
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#define CONFIG_ENV_SPI_BUS 0 |
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#define CONFIG_ENV_SPI_CS 0 |
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#define CONFIG_ENV_SPI_MAX_HZ 10000000 |
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#define CONFIG_ENV_SPI_MODE 0 |
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/*
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* General PCI |
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* Memory space is mapped 1-1, but I/O space must start from 0. |
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*/ |
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#ifdef CONFIG_PCI |
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/* controller 1, direct to uli, tgtid 3, Base address 20000 */ |
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#ifdef CONFIG_PCIE1 |
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#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
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#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull |
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
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#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 |
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#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull |
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
||||
#endif |
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ |
||||
#ifdef CONFIG_PCIE2 |
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull |
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 |
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull |
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
||||
#endif |
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ |
||||
#ifdef CONFIG_PCIE3 |
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull |
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 |
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull |
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
||||
#endif |
||||
|
||||
/* controller 4, Base address 203000 */ |
||||
#ifdef CONFIG_PCIE4 |
||||
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 |
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 |
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull |
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ |
||||
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 |
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 |
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull |
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ |
||||
#endif |
||||
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */ |
||||
#define CONFIG_E1000 |
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif /* CONFIG_PCI */ |
||||
|
||||
/* SATA */ |
||||
#define CONFIG_FSL_SATA_V2 |
||||
#ifdef CONFIG_FSL_SATA_V2 |
||||
#define CONFIG_LIBATA |
||||
#define CONFIG_FSL_SATA |
||||
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 1 |
||||
#define CONFIG_SATA1 |
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA |
||||
|
||||
#define CONFIG_LBA48 |
||||
#define CONFIG_CMD_SATA |
||||
#define CONFIG_DOS_PARTITION |
||||
#define CONFIG_CMD_EXT2 |
||||
#endif |
||||
|
||||
/*
|
||||
* USB |
||||
*/ |
||||
#define CONFIG_HAS_FSL_DR_USB |
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB |
||||
#define CONFIG_USB_EHCI |
||||
|
||||
#ifdef CONFIG_USB_EHCI |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_USB_EHCI_FSL |
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
||||
#define CONFIG_CMD_EXT2 |
||||
#endif |
||||
#endif |
||||
|
||||
#define CONFIG_MMC |
||||
|
||||
#ifdef CONFIG_MMC |
||||
#define CONFIG_FSL_ESDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
||||
#define CONFIG_CMD_MMC |
||||
#define CONFIG_GENERIC_MMC |
||||
#define CONFIG_CMD_EXT2 |
||||
#define CONFIG_CMD_FAT |
||||
#define CONFIG_DOS_PARTITION |
||||
#endif |
||||
|
||||
/* Qman/Bman */ |
||||
#ifndef CONFIG_NOBQFMAN |
||||
#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 25 |
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 |
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull |
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 |
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 25 |
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 |
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull |
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 |
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_SYS_DPAA_PME |
||||
|
||||
/* Default address of microcode for the Linux Fman driver */ |
||||
#if defined(CONFIG_SPIFLASH) |
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after |
||||
* env, so we got 0x110000. |
||||
*/ |
||||
#define CONFIG_SYS_QE_FW_IN_SPIFLASH |
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 |
||||
#elif defined(CONFIG_SDCARD) |
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is |
||||
* about 825KB (1650 blocks), Env is stored after the image, and the env size is |
||||
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. |
||||
*/ |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_MMC |
||||
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) |
||||
#elif defined(CONFIG_NAND) |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND |
||||
#define CONFIG_SYS_FMAN_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) |
||||
#else |
||||
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 |
||||
#endif |
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 |
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) |
||||
#endif /* CONFIG_NOBQFMAN */ |
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN |
||||
#define CONFIG_FMAN_ENET |
||||
#define CONFIG_PHY_VITESSE |
||||
#define CONFIG_PHY_REALTEK |
||||
#endif |
||||
|
||||
#ifdef CONFIG_FMAN_ENET |
||||
#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 |
||||
#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 |
||||
|
||||
#define CONFIG_MII /* MII PHY management */ |
||||
#define CONFIG_ETHPRIME "FM1@DTSEC4" |
||||
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment |
||||
*/ |
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */ |
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
||||
|
||||
/*
|
||||
* Command line configuration. |
||||
*/ |
||||
#include <config_cmd_default.h> |
||||
|
||||
#define CONFIG_CMD_DATE |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_ELF |
||||
#define CONFIG_CMD_ERRATA |
||||
#define CONFIG_CMD_GREPENV |
||||
#define CONFIG_CMD_IRQ |
||||
#define CONFIG_CMD_I2C |
||||
#define CONFIG_CMD_MII |
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_REGINFO |
||||
#define CONFIG_CMD_SETEXPR |
||||
|
||||
#ifdef CONFIG_PCI |
||||
#define CONFIG_CMD_PCI |
||||
#define CONFIG_CMD_NET |
||||
#endif |
||||
|
||||
/*
|
||||
* Miscellaneous configurable options |
||||
*/ |
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */ |
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
||||
#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ |
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
||||
#else |
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
||||
#endif |
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ |
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data |
||||
* have to be in the first 64 MB of memory, since this is |
||||
* the maximum mapped by the Linux kernel during initialization. |
||||
*/ |
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ |
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
||||
|
||||
#ifdef CONFIG_CMD_KGDB |
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
||||
#endif |
||||
|
||||
/*
|
||||
* Environment Configuration |
||||
*/ |
||||
#define CONFIG_ROOTPATH "/opt/nfsroot" |
||||
#define CONFIG_BOOTFILE "uImage" |
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ |
||||
|
||||
/* default location for tftp and bootm */ |
||||
#define CONFIG_LOADADDR 1000000 |
||||
|
||||
#define CONFIG_BOOTDELAY 10 /*-1 disables auto-boot*/ |
||||
|
||||
#define CONFIG_BAUDRATE 115200 |
||||
|
||||
#define __USB_PHY_TYPE utmi |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
|
||||
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=t1040rdb_pi/ramdisk.uboot\0" \
|
||||
"fdtaddr=c00000\0" \
|
||||
"fdtfile=t1040rdb_pi/t1040rdb_pi.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"c=ffe\0" |
||||
|
||||
#define CONFIG_LINUX \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_HDBOOT \ |
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr" |
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \ |
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr" |
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX |
||||
|
||||
#ifdef CONFIG_SECURE_BOOT |
||||
#include <asm/fsl_secure_boot.h> |
||||
#endif |
||||
|
||||
#endif /* __CONFIG_H */ |
||||
Loading…
Reference in new issue