diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index c7ed161..001f2c1 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -2172,11 +2172,6 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	unsigned long i;
 	unsigned long bank_0_populated = 0;
 	phys_size_t total_size = 0;
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
-    defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
-    defined(CONFIG_460SX)
-	unsigned long val;
-#endif
 
 	/*------------------------------------------------------------------
 	 * Reset the rank_base_address.
@@ -2257,7 +2252,6 @@ static void program_memory_queue(unsigned long *dimm_populated,
 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
     defined(CONFIG_460SX)
-
 	/*
 	 * Enable high bandwidth access
 	 * This is currently not used, but with this setup
@@ -2270,15 +2264,11 @@ static void program_memory_queue(unsigned long *dimm_populated,
 	/*
 	 * Set optimal value for Memory Queue HB/LL Configuration registers
 	 */
-
-	val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
-	mtdcr(SDRAM_CONF1HB, val);
-
-	val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
-	mtdcr(SDRAM_CONF1LL, val);
-
-	val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
-	mtdcr(SDRAM_CONFPATHB, val);
+	mtdcr(SDRAM_CONF1HB, mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR |
+	      SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE);
+	mtdcr(SDRAM_CONF1LL, mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR |
+	      SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE);
+	mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
 #endif
 }
 
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index 281819a..dee9807 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -138,9 +138,7 @@ void reconfigure_pll(u32 new_cpu_freq)
 void
 cpu_init_f (void)
 {
-#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \
-    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX)   || \
-    defined(CONFIG_460GT) || defined(CONFIG_460SX)
+#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX)
 	u32 val;
 #endif
 
@@ -304,16 +302,17 @@ cpu_init_f (void)
 	mtsdr(SDR0_USB2HOST_CFG, val);
 #endif /* CONFIG_460EX */
 
-#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
+#if defined(CONFIG_405EX) || \
+    defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
     defined(CONFIG_460EX) || defined(CONFIG_460GT)  || \
-    defined(CONFIG_405EX) || defined(CONFIG_460SX)
+    defined(CONFIG_460SX)
 	/*
 	 * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read
 	 */
-	val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
-	mtdcr(plb0_acr, val);
-	val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
-	mtdcr(plb1_acr, val);
+	mtdcr(plb0_acr, (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) |
+	      plb0_acr_rdp_4deep);
+	mtdcr(plb1_acr, (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) |
+	      plb1_acr_rdp_4deep);
 #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */
 }
 
diff --git a/include/ppc4xx.h b/include/ppc4xx.h
index e1613dd..59a3b06 100644
--- a/include/ppc4xx.h
+++ b/include/ppc4xx.h
@@ -56,8 +56,8 @@
 
 #define PLB_ARBITER_BASE		0x80
 
-#define plb0_revid			(PLB_ARBITER_BASE+ 0x00)
-#define plb0_acr			(PLB_ARBITER_BASE+ 0x01)
+#define plb0_revid			(PLB_ARBITER_BASE + 0x00)
+#define plb0_acr			(PLB_ARBITER_BASE + 0x01)
 #define plb0_acr_ppm_mask		0xF0000000
 #define plb0_acr_ppm_fixed		0x00000000
 #define plb0_acr_ppm_fair		0xD0000000
@@ -73,13 +73,13 @@
 #define plb0_acr_wrp_disabled		0x00000000
 #define plb0_acr_wrp_2deep		0x01000000
 
-#define plb0_besrl			(PLB_ARBITER_BASE+ 0x02)
-#define plb0_besrh			(PLB_ARBITER_BASE+ 0x03)
-#define plb0_bearl			(PLB_ARBITER_BASE+ 0x04)
-#define plb0_bearh			(PLB_ARBITER_BASE+ 0x05)
-#define plb0_ccr			(PLB_ARBITER_BASE+ 0x08)
+#define plb0_besrl			(PLB_ARBITER_BASE + 0x02)
+#define plb0_besrh			(PLB_ARBITER_BASE + 0x03)
+#define plb0_bearl			(PLB_ARBITER_BASE + 0x04)
+#define plb0_bearh			(PLB_ARBITER_BASE + 0x05)
+#define plb0_ccr			(PLB_ARBITER_BASE + 0x08)
 
-#define plb1_acr			(PLB_ARBITER_BASE+ 0x09)
+#define plb1_acr			(PLB_ARBITER_BASE + 0x09)
 #define plb1_acr_ppm_mask		0xF0000000
 #define plb1_acr_ppm_fixed		0x00000000
 #define plb1_acr_ppm_fair		0xD0000000
@@ -95,10 +95,10 @@
 #define plb1_acr_wrp_disabled		0x00000000
 #define plb1_acr_wrp_2deep		0x01000000
 
-#define plb1_besrl			(PLB_ARBITER_BASE+ 0x0A)
-#define plb1_besrh			(PLB_ARBITER_BASE+ 0x0B)
-#define plb1_bearl			(PLB_ARBITER_BASE+ 0x0C)
-#define plb1_bearh			(PLB_ARBITER_BASE+ 0x0D)
+#define plb1_besrl			(PLB_ARBITER_BASE + 0x0A)
+#define plb1_besrh			(PLB_ARBITER_BASE + 0x0B)
+#define plb1_bearl			(PLB_ARBITER_BASE + 0x0C)
+#define plb1_bearh			(PLB_ARBITER_BASE + 0x0D)
 
 #endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/