commit
f5fd45ff64
@ -0,0 +1,48 @@ |
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/* |
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* Copyright 2016 Toradex AG |
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* |
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* SPDX-License-Identifier: GPL-2.0+ or X11 |
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*/ |
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|
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/dts-v1/; |
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#include "vf.dtsi" |
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|
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/ { |
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model = "Phytec phyCORE-Vybrid"; |
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compatible = "phytec,pcm052", "fsl,vf610"; |
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|
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chosen { |
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stdout-path = &uart1; |
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}; |
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|
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aliases { |
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spi0 = &qspi0; |
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}; |
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|
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}; |
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|
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&uart1 { |
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status = "okay"; |
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}; |
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|
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&qspi0 { |
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bus-num = <0>; |
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num-cs = <2>; |
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status = "okay"; |
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|
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qflash0: spi_flash@0 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <108000000>; |
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reg = <0>; |
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}; |
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|
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qflash1: spi_flash@1 { |
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#address-cells = <1>; |
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#size-cells = <1>; |
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compatible = "spi-flash"; |
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spi-max-frequency = <66000000>; |
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reg = <1>; |
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}; |
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}; |
@ -0,0 +1,938 @@ |
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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*/ |
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|
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#ifndef __DTS_IMX6UL_PINFUNC_H |
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#define __DTS_IMX6UL_PINFUNC_H |
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|
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/*
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* The pin function ID is a tuple of |
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* <mux_reg conf_reg input_reg mux_mode input_val> |
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*/ |
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#define MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x0014 0x02a0 0x0000 5 0 |
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#define MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x0018 0x02a4 0x0000 5 0 |
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|
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#define MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x001c 0x02a8 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0020 0x02ac 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0024 0x02b0 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0028 0x02b4 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x002c 0x02b8 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0030 0x02bc 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0034 0x02c0 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0038 0x02c4 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x003c 0x02c8 0x0000 5 0 |
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#define MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0040 0x02cc 0x0000 5 0 |
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|
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#define MX6UL_PAD_JTAG_MOD__SJC_MOD 0x0044 0x02d0 0x0000 0 0 |
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#define MX6UL_PAD_JTAG_MOD__GPT2_CLK 0x0044 0x02d0 0x05a0 1 0 |
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#define MX6UL_PAD_JTAG_MOD__SPDIF_OUT 0x0044 0x02d0 0x0000 2 0 |
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#define MX6UL_PAD_JTAG_MOD__ENET1_REF_CLK_25M 0x0044 0x02d0 0x0000 3 0 |
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#define MX6UL_PAD_JTAG_MOD__CCM_PMIC_RDY 0x0044 0x02d0 0x04c0 4 0 |
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#define MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0044 0x02d0 0x0000 5 0 |
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#define MX6UL_PAD_JTAG_MOD__SDMA_EXT_EVENT00 0x0044 0x02d0 0x0000 6 0 |
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#define MX6UL_PAD_JTAG_TMS__SJC_TMS 0x0048 0x02d4 0x0000 0 0 |
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#define MX6UL_PAD_JTAG_TMS__GPT2_CAPTURE1 0x0048 0x02d4 0x0598 1 0 |
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#define MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x0048 0x02d4 0x0000 2 0 |
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#define MX6UL_PAD_JTAG_TMS__CCM_CLKO1 0x0048 0x02d4 0x0000 3 0 |
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#define MX6UL_PAD_JTAG_TMS__CCM_WAIT 0x0048 0x02d4 0x0000 4 0 |
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#define MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x0048 0x02d4 0x0000 5 0 |
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#define MX6UL_PAD_JTAG_TMS__SDMA_EXT_EVENT01 0x0048 0x02d4 0x0000 6 0 |
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#define MX6UL_PAD_JTAG_TMS__EPIT1_OUT 0x0048 0x02d4 0x0000 8 0 |
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#define MX6UL_PAD_JTAG_TDO__SJC_TDO 0x004c 0x02d8 0x0000 0 0 |
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#define MX6UL_PAD_JTAG_TDO__GPT2_CAPTURE2 0x004c 0x02d8 0x059c 1 0 |
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#define MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x004c 0x02d8 0x05fc 2 0 |
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#define MX6UL_PAD_JTAG_TDO__CCM_CLKO2 0x004c 0x02d8 0x0000 3 0 |
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#define MX6UL_PAD_JTAG_TDO__CCM_STOP 0x004c 0x02d8 0x0000 4 0 |
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#define MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x004c 0x02d8 0x0000 5 0 |
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#define MX6UL_PAD_JTAG_TDO__MQS_RIGHT 0x004c 0x02d8 0x0000 6 0 |
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#define MX6UL_PAD_JTAG_TDO__EPIT2_OUT 0x004c 0x02d8 0x0000 8 0 |
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#define MX6UL_PAD_JTAG_TDI__SJC_TDI 0x0050 0x02dc 0x0000 0 0 |
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#define MX6UL_PAD_JTAG_TDI__GPT2_COMPARE1 0x0050 0x02dc 0x0000 1 0 |
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#define MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0050 0x02dc 0x05f8 2 0 |
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#define MX6UL_PAD_JTAG_TDI__PWM6_OUT 0x0050 0x02dc 0x0000 4 0 |
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#define MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x0050 0x02dc 0x0000 5 0 |
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#define MX6UL_PAD_JTAG_TDI__MQS_LEFT 0x0050 0x02dc 0x0000 6 0 |
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#define MX6UL_PAD_JTAG_TDI__SIM1_POWER_FAIL 0x0050 0x02dc 0x0000 8 0 |
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#define MX6UL_PAD_JTAG_TCK__SJC_TCK 0x0054 0x02e0 0x0000 0 0 |
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#define MX6UL_PAD_JTAG_TCK__GPT2_COMPARE2 0x0054 0x02e0 0x0000 1 0 |
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#define MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0054 0x02e0 0x05f4 2 0 |
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#define MX6UL_PAD_JTAG_TCK__PWM7_OUT 0x0054 0x02e0 0x0000 4 0 |
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#define MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x0054 0x02e0 0x0000 5 0 |
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#define MX6UL_PAD_JTAG_TCK__SIM2_POWER_FAIL 0x0054 0x02e0 0x0000 8 0 |
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#define MX6UL_PAD_JTAG_TRST_B__SJC_TRSTB 0x0058 0x02e4 0x0000 0 0 |
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#define MX6UL_PAD_JTAG_TRST_B__GPT2_COMPARE3 0x0058 0x02e4 0x0000 1 0 |
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#define MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0058 0x02e4 0x0000 2 0 |
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#define MX6UL_PAD_JTAG_TRST_B__PWM8_OUT 0x0058 0x02e4 0x0000 4 0 |
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#define MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x0058 0x02e4 0x0000 5 0 |
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#define MX6UL_PAD_JTAG_TRST_B__CAAM_RNG_OSC_OBS 0x0058 0x02e4 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x005c 0x02e8 0x05ac 0 1 |
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#define MX6UL_PAD_GPIO1_IO00__GPT1_CAPTURE1 0x005c 0x02e8 0x058c 1 0 |
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#define MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x005c 0x02e8 0x04b8 2 0 |
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#define MX6UL_PAD_GPIO1_IO00__ENET1_REF_CLK1 0x005c 0x02e8 0x0574 3 0 |
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#define MX6UL_PAD_GPIO1_IO00__MQS_RIGHT 0x005c 0x02e8 0x0000 4 0 |
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#define MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x005c 0x02e8 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO00__ENET1_1588_EVENT0_IN 0x005c 0x02e8 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO00__SRC_SYSTEM_RESET 0x005c 0x02e8 0x0000 7 0 |
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#define MX6UL_PAD_GPIO1_IO00__WDOG3_WDOG_B 0x005c 0x02e8 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x0060 0x02ec 0x05b0 0 1 |
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#define MX6UL_PAD_GPIO1_IO01__GPT1_COMPARE1 0x0060 0x02ec 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO01__USB_OTG1_OC 0x0060 0x02ec 0x0664 2 0 |
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#define MX6UL_PAD_GPIO1_IO01__ENET2_REF_CLK2 0x0060 0x02ec 0x057c 3 0 |
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#define MX6UL_PAD_GPIO1_IO01__MQS_LEFT 0x0060 0x02ec 0x0000 4 0 |
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#define MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x0060 0x02ec 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO01__ENET1_1588_EVENT0_OUT 0x0060 0x02ec 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO01__SRC_EARLY_RESET 0x0060 0x02ec 0x0000 7 0 |
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#define MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x0060 0x02ec 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO02__I2C1_SCL 0x0064 0x02f0 0x05a4 0 0 |
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#define MX6UL_PAD_GPIO1_IO02__GPT1_COMPARE2 0x0064 0x02f0 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO02__USB_OTG2_PWR 0x0064 0x02f0 0x0000 2 0 |
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#define MX6UL_PAD_GPIO1_IO02__ENET1_REF_CLK_25M 0x0064 0x02f0 0x0000 3 0 |
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#define MX6UL_PAD_GPIO1_IO02__USDHC1_WP 0x0064 0x02f0 0x066c 4 0 |
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#define MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0064 0x02f0 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO02__SDMA_EXT_EVENT00 0x0064 0x02f0 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO02__SRC_ANY_PU_RESET 0x0064 0x02f0 0x0000 7 0 |
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#define MX6UL_PAD_GPIO1_IO02__UART1_DCE_TX 0x0064 0x02f0 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO02__UART1_DTE_RX 0x0064 0x02f0 0x0624 8 0 |
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#define MX6UL_PAD_GPIO1_IO03__I2C1_SDA 0x0068 0x02f4 0x05a8 0 1 |
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#define MX6UL_PAD_GPIO1_IO03__GPT1_COMPARE3 0x0068 0x02f4 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO03__USB_OTG2_OC 0x0068 0x02f4 0x0660 2 0 |
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#define MX6UL_PAD_GPIO1_IO03__USDHC1_CD_B 0x0068 0x02f4 0x0668 4 0 |
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#define MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x0068 0x02f4 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO03__CCM_DI0_eXT_CLK 0x0068 0x02f4 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO03__SRC_TESTER_ACK 0x0068 0x02f4 0x0000 7 0 |
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#define MX6UL_PAD_GPIO1_IO03__UART1_DTE_TX 0x0068 0x02f4 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO03__UART1_DCE_RX 0x0068 0x02f4 0x0624 8 1 |
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#define MX6UL_PAD_GPIO1_IO04__ENET1_REF_CLK1 0x006c 0x02f8 0x0574 0 1 |
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#define MX6UL_PAD_GPIO1_IO04__PWM3_OUT 0x006c 0x02f8 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO04__USB_OTG1_PWR 0x006c 0x02f8 0x0000 2 0 |
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#define MX6UL_PAD_GPIO1_IO04__USDHC1_RESET_B 0x006c 0x02f8 0x0000 4 0 |
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#define MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x006c 0x02f8 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO04__ENET2_1588_EVENT0_IN 0x006c 0x02f8 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x006c 0x02f8 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x006c 0x02f8 0x0644 8 2 |
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#define MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2 0x0070 0x02fc 0x057c 0 1 |
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#define MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x0070 0x02fc 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO05__ANATOP_OTG2_ID 0x0070 0x02fc 0x04bc 2 0 |
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#define MX6UL_PAD_GPIO1_IO05__CSI_FIELD 0x0070 0x02fc 0x0530 3 0 |
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#define MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x0070 0x02fc 0x0000 4 0 |
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#define MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x0070 0x02fc 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO05__ENET2_1588_EVENT0_OUT 0x0070 0x02fc 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0070 0x02fc 0x0644 8 3 |
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#define MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x0070 0x02fc 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x0074 0x0300 0x0578 0 0 |
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#define MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x0074 0x0300 0x0580 1 0 |
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#define MX6UL_PAD_GPIO1_IO06__USB_OTG_PWR_WAKE 0x0074 0x0300 0x0000 2 0 |
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#define MX6UL_PAD_GPIO1_IO06__CSI_MCLK 0x0074 0x0300 0x0000 3 0 |
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#define MX6UL_PAD_GPIO1_IO06__USDHC2_WP 0x0074 0x0300 0x069c 4 0 |
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#define MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0074 0x0300 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO06__CCM_WAIT 0x0074 0x0300 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO06__CCM_REF_EN_B 0x0074 0x0300 0x0000 7 0 |
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#define MX6UL_PAD_GPIO1_IO06__UART1_DCE_CTS 0x0074 0x0300 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO06__UART1_DTE_RTS 0x0074 0x0300 0x0620 8 0 |
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#define MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0078 0x0304 0x0000 0 0 |
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#define MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x0078 0x0304 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO07__USB_OTG_HOST_MODE 0x0078 0x0304 0x0000 2 0 |
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#define MX6UL_PAD_GPIO1_IO07__CSI_PIXCLK 0x0078 0x0304 0x0528 3 0 |
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#define MX6UL_PAD_GPIO1_IO07__USDHC2_CD_B 0x0078 0x0304 0x0674 4 1 |
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#define MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0078 0x0304 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO07__CCM_STOP 0x0078 0x0304 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO07__UART1_DCE_RTS 0x0078 0x0304 0x0620 8 1 |
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#define MX6UL_PAD_GPIO1_IO07__UART1_DTE_CTS 0x0078 0x0304 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x007c 0x0308 0x0000 0 0 |
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#define MX6UL_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x007c 0x0308 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO08__SPDIF_OUT 0x007c 0x0308 0x0000 2 0 |
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#define MX6UL_PAD_GPIO1_IO08__CSI_VSYNC 0x007c 0x0308 0x052c 3 1 |
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#define MX6UL_PAD_GPIO1_IO08__USDHC2_VSELECT 0x007c 0x0308 0x0000 4 0 |
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#define MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x007c 0x0308 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x007c 0x0308 0x04c0 6 1 |
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#define MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x007c 0x0308 0x0640 8 1 |
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#define MX6UL_PAD_GPIO1_IO08__UART5_DTE_CTS 0x007c 0x0308 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO09__PWM2_OUT 0x0080 0x030c 0x0000 0 0 |
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#define MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x0080 0x030c 0x0000 1 0 |
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#define MX6UL_PAD_GPIO1_IO09__SPDIF_IN 0x0080 0x030c 0x0618 2 0 |
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#define MX6UL_PAD_GPIO1_IO09__CSI_HSYNC 0x0080 0x030c 0x0524 3 1 |
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#define MX6UL_PAD_GPIO1_IO09__USDHC2_RESET_B 0x0080 0x030c 0x0000 4 0 |
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#define MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0080 0x030c 0x0000 5 0 |
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#define MX6UL_PAD_GPIO1_IO09__USDHC1_RESET_B 0x0080 0x030c 0x0000 6 0 |
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#define MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0080 0x030c 0x0000 8 0 |
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#define MX6UL_PAD_GPIO1_IO09__UART5_DTE_RTS 0x0080 0x030c 0x0640 8 2 |
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#define MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0084 0x0310 0x0000 0 0 |
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#define MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x0084 0x0310 0x0624 0 2 |
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#define MX6UL_PAD_UART1_TX_DATA__ENET1_RDATA02 0x0084 0x0310 0x0000 1 0 |
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#define MX6UL_PAD_UART1_TX_DATA__I2C3_SCL 0x0084 0x0310 0x05b4 2 0 |
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#define MX6UL_PAD_UART1_TX_DATA__CSI_DATA02 0x0084 0x0310 0x04c4 3 1 |
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#define MX6UL_PAD_UART1_TX_DATA__GPT1_COMPARE1 0x0084 0x0310 0x0000 4 0 |
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#define MX6UL_PAD_UART1_TX_DATA__GPIO1_IO16 0x0084 0x0310 0x0000 5 0 |
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#define MX6UL_PAD_UART1_TX_DATA__SPDIF_OUT 0x0084 0x0310 0x0000 8 0 |
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#define MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0088 0x0314 0x0624 0 3 |
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#define MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x0088 0x0314 0x0000 0 0 |
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#define MX6UL_PAD_UART1_RX_DATA__ENET1_RDATA03 0x0088 0x0314 0x0000 1 0 |
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#define MX6UL_PAD_UART1_RX_DATA__I2C3_SDA 0x0088 0x0314 0x05b8 2 0 |
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#define MX6UL_PAD_UART1_RX_DATA__CSI_DATA03 0x0088 0x0314 0x04c8 3 1 |
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#define MX6UL_PAD_UART1_RX_DATA__GPT1_CLK 0x0088 0x0314 0x0594 4 0 |
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#define MX6UL_PAD_UART1_RX_DATA__GPIO1_IO17 0x0088 0x0314 0x0000 5 0 |
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#define MX6UL_PAD_UART1_RX_DATA__SPDIF_IN 0x0088 0x0314 0x0618 8 1 |
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#define MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x008c 0x0318 0x0000 0 0 |
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#define MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x008c 0x0318 0x0620 0 2 |
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#define MX6UL_PAD_UART1_CTS_B__ENET1_RX_CLK 0x008c 0x0318 0x0000 1 0 |
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#define MX6UL_PAD_UART1_CTS_B__USDHC1_WP 0x008c 0x0318 0x066c 2 1 |
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#define MX6UL_PAD_UART1_CTS_B__CSI_DATA04 0x008c 0x0318 0x04d8 3 0 |
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#define MX6UL_PAD_UART1_CTS_B__ENET2_1588_EVENT1_IN 0x008c 0x0318 0x0000 4 0 |
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#define MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x008c 0x0318 0x0000 5 0 |
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#define MX6UL_PAD_UART1_CTS_B__USDHC2_WP 0x008c 0x0318 0x069c 8 1 |
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#define MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0090 0x031c 0x0620 0 3 |
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#define MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x0090 0x031c 0x0000 0 0 |
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#define MX6UL_PAD_UART1_RTS_B__ENET1_TX_ER 0x0090 0x031c 0x0000 1 0 |
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#define MX6UL_PAD_UART1_RTS_B__USDHC1_CD_B 0x0090 0x031c 0x0668 2 1 |
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#define MX6UL_PAD_UART1_RTS_B__CSI_DATA05 0x0090 0x031c 0x04cc 3 1 |
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#define MX6UL_PAD_UART1_RTS_B__ENET2_1588_EVENT1_OUT 0x0090 0x031c 0x0000 4 0 |
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#define MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0090 0x031c 0x0000 5 0 |
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#define MX6UL_PAD_UART1_RTS_B__USDHC2_CD_B 0x0090 0x031c 0x0674 8 2 |
||||
#define MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0094 0x0320 0x0000 0 0 |
||||
#define MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x0094 0x0320 0x062c 0 0 |
||||
#define MX6UL_PAD_UART2_TX_DATA__ENET1_TDATA02 0x0094 0x0320 0x0000 1 0 |
||||
#define MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x0094 0x0320 0x05bc 2 0 |
||||
#define MX6UL_PAD_UART2_TX_DATA__CSI_DATA06 0x0094 0x0320 0x04dc 3 0 |
||||
#define MX6UL_PAD_UART2_TX_DATA__GPT1_CAPTURE1 0x0094 0x0320 0x058c 4 1 |
||||
#define MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20 0x0094 0x0320 0x0000 5 0 |
||||
#define MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0 0x0094 0x0320 0x0000 8 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0098 0x0324 0x062c 0 1 |
||||
#define MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x0098 0x0324 0x0000 0 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__ENET1_TDATA03 0x0098 0x0324 0x0000 1 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x0098 0x0324 0x05c0 2 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__CSI_DATA07 0x0098 0x0324 0x04e0 3 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__GPT1_CAPTURE2 0x0098 0x0324 0x0590 4 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__GPIO1_IO21 0x0098 0x0324 0x0000 5 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__SJC_DONE 0x0098 0x0324 0x0000 7 0 |
||||
#define MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK 0x0098 0x0324 0x0554 8 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x009c 0x0328 0x0000 0 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x009c 0x0328 0x0628 0 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__ENET1_CRS 0x009c 0x0328 0x0000 1 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x009c 0x0328 0x0000 2 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__CSI_DATA08 0x009c 0x0328 0x04e4 3 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__GPT1_COMPARE2 0x009c 0x0328 0x0000 4 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__GPIO1_IO22 0x009c 0x0328 0x0000 5 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__SJC_DE_B 0x009c 0x0328 0x0000 7 0 |
||||
#define MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI 0x009c 0x0328 0x055c 8 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x00a0 0x032c 0x0628 0 1 |
||||
#define MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x00a0 0x032c 0x0000 0 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__ENET1_COL 0x00a0 0x032c 0x0000 1 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x00a0 0x032c 0x0588 2 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__CSI_DATA09 0x00a0 0x032c 0x04e8 3 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__GPT1_COMPARE3 0x00a0 0x032c 0x0000 4 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__GPIO1_IO23 0x00a0 0x032c 0x0000 5 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__SJC_FAIL 0x00a0 0x032c 0x0000 7 0 |
||||
#define MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO 0x00a0 0x032c 0x0558 8 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x00a4 0x0330 0x0000 0 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__UART3_DTE_RX 0x00a4 0x0330 0x0634 0 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__ENET2_RDATA02 0x00a4 0x0330 0x0000 1 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__SIM1_PORT0_PD 0x00a4 0x0330 0x0000 2 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__CSI_DATA01 0x00a4 0x0330 0x0000 3 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x00a4 0x0330 0x0000 4 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x00a4 0x0330 0x0628 4 2 |
||||
#define MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x00a4 0x0330 0x0000 5 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__SJC_JTAG_ACT 0x00a4 0x0330 0x0000 7 0 |
||||
#define MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x00a4 0x0330 0x04b8 8 1 |
||||
#define MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x00a8 0x0334 0x0634 0 1 |
||||
#define MX6UL_PAD_UART3_RX_DATA__UART3_DTE_TX 0x00a8 0x0334 0x0000 0 0 |
||||
#define MX6UL_PAD_UART3_RX_DATA__ENET2_RDATA03 0x00a8 0x0334 0x0000 1 0 |
||||
#define MX6UL_PAD_UART3_RX_DATA__SIM2_PORT0_PD 0x00a8 0x0334 0x0000 2 0 |
||||
#define MX6UL_PAD_UART3_RX_DATA__CSI_DATA00 0x00a8 0x0334 0x0000 3 0 |
||||
#define MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x00a8 0x0334 0x0628 4 3 |
||||
#define MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x00a8 0x0334 0x0000 4 0 |
||||
#define MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x00a8 0x0334 0x0000 5 0 |
||||
#define MX6UL_PAD_UART3_RX_DATA__EPIT1_OUT 0x00a8 0x0334 0x0000 8 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x00ac 0x0338 0x0000 0 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__UART3_DTE_RTS 0x00ac 0x0338 0x0630 0 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__ENET2_RX_CLK 0x00ac 0x0338 0x0000 1 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x00ac 0x0338 0x0000 2 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__CSI_DATA10 0x00ac 0x0338 0x0000 3 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__ENET1_1588_EVENT1_IN 0x00ac 0x0338 0x0000 4 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x00ac 0x0338 0x0000 5 0 |
||||
#define MX6UL_PAD_UART3_CTS_B__EPIT2_OUT 0x00ac 0x0338 0x0000 8 0 |
||||
#define MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x00b0 0x033c 0x0630 0 1 |
||||
#define MX6UL_PAD_UART3_RTS_B__UART3_DTE_CTS 0x00b0 0x033c 0x0000 0 0 |
||||
#define MX6UL_PAD_UART3_RTS_B__ENET2_TX_ER 0x00b0 0x033c 0x0000 1 0 |
||||
#define MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x00b0 0x033c 0x0584 2 0 |
||||
#define MX6UL_PAD_UART3_RTS_B__CSI_DATA11 0x00b0 0x033c 0x0000 3 0 |
||||
#define MX6UL_PAD_UART3_RTS_B__ENET1_1588_EVENT1_OUT 0x00b0 0x033c 0x0000 4 0 |
||||
#define MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x00b0 0x033c 0x0000 5 0 |
||||
#define MX6UL_PAD_UART3_RTS_B__WDOG1_WDOG_B 0x00b0 0x033c 0x0000 8 0 |
||||
#define MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x00b4 0x0340 0x0000 0 0 |
||||
#define MX6UL_PAD_UART4_TX_DATA__UART4_DTE_RX 0x00b4 0x0340 0x063c 0 0 |
||||
#define MX6UL_PAD_UART4_TX_DATA__ENET2_TDATA02 0x00b4 0x0340 0x0000 1 0 |
||||
#define MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x00b4 0x0340 0x05a4 2 1 |
||||
#define MX6UL_PAD_UART4_TX_DATA__CSI_DATA12 0x00b4 0x0340 0x0000 3 0 |
||||
#define MX6UL_PAD_UART4_TX_DATA__CSU_CSU_ALARM_AUT02 0x00b4 0x0340 0x0000 4 0 |
||||
#define MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x00b4 0x0340 0x0000 5 0 |
||||
#define MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x00b4 0x0340 0x0544 8 1 |
||||
#define MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x00b8 0x0344 0x063c 0 1 |
||||
#define MX6UL_PAD_UART4_RX_DATA__UART4_DTE_TX 0x00b8 0x0344 0x0000 0 0 |
||||
#define MX6UL_PAD_UART4_RX_DATA__ENET2_TDATA03 0x00b8 0x0344 0x0000 1 0 |
||||
#define MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x00b8 0x0344 0x05a8 2 2 |
||||
#define MX6UL_PAD_UART4_RX_DATA__CSI_DATA13 0x00b8 0x0344 0x0000 3 0 |
||||
#define MX6UL_PAD_UART4_RX_DATA__CSU_CSU_ALARM_AUT01 0x00b8 0x0344 0x0000 4 0 |
||||
#define MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x00b8 0x0344 0x0000 5 0 |
||||
#define MX6UL_PAD_UART4_RX_DATA__ECSPI2_SS0 0x00b8 0x0344 0x0000 8 0 |
||||
#define MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x00bc 0x0348 0x0000 5 0 |
||||
#define MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x00bc 0x0348 0x054c 8 0 |
||||
#define MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX 0x00bc 0x0348 0x0000 0 0 |
||||
#define MX6UL_PAD_UART5_TX_DATA__UART5_DTE_RX 0x00bc 0x0348 0x0644 0 4 |
||||
#define MX6UL_PAD_UART5_TX_DATA__ENET2_CRS 0x00bc 0x0348 0x0000 1 0 |
||||
#define MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x00bc 0x0348 0x05ac 2 2 |
||||
#define MX6UL_PAD_UART5_TX_DATA__CSI_DATA14 0x00bc 0x0348 0x0000 3 0 |
||||
#define MX6UL_PAD_UART5_TX_DATA__CSU_CSU_ALARM_AUT00 0x00bc 0x0348 0x0000 4 0 |
||||
#define MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX 0x00c0 0x034c 0x0644 0 5 |
||||
#define MX6UL_PAD_UART5_RX_DATA__UART5_DTE_TX 0x00c0 0x034c 0x0000 0 0 |
||||
#define MX6UL_PAD_UART5_RX_DATA__ENET2_COL 0x00c0 0x034c 0x0000 1 0 |
||||
#define MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x00c0 0x034c 0x05b0 2 2 |
||||
#define MX6UL_PAD_UART5_RX_DATA__CSI_DATA15 0x00c0 0x034c 0x0000 3 0 |
||||
#define MX6UL_PAD_UART5_RX_DATA__CSU_CSU_INT_DEB 0x00c0 0x034c 0x0000 4 0 |
||||
#define MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x00c0 0x034c 0x0000 5 0 |
||||
#define MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x00c0 0x034c 0x0548 8 1 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x00c4 0x0350 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DCE_RTS 0x00c4 0x0350 0x0638 1 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__UART4_DTE_CTS 0x00c4 0x0350 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__PWM1_OUT 0x00c4 0x0350 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__CSI_DATA16 0x00c4 0x0350 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x00c4 0x0350 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x00c4 0x0350 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__KPP_ROW00 0x00c4 0x0350 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA0__USDHC1_LCTL 0x00c4 0x0350 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x00c8 0x0354 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DCE_CTS 0x00c8 0x0354 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__UART4_DTE_RTS 0x00c8 0x0354 0x0638 1 1 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__PWM2_OUT 0x00c8 0x0354 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__CSI_DATA17 0x00c8 0x0354 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x00c8 0x0354 0x0584 4 1 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x00c8 0x0354 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__KPP_COL00 0x00c8 0x0354 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_RX_DATA1__USDHC2_LCTL 0x00c8 0x0354 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x00cc 0x0358 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_RX_EN__UART5_DCE_RTS 0x00cc 0x0358 0x0640 1 3 |
||||
#define MX6UL_PAD_ENET1_RX_EN__UART5_DTE_CTS 0x00cc 0x0358 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_RX_EN__CSI_DATA18 0x00cc 0x0358 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x00cc 0x0358 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x00cc 0x0358 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_RX_EN__KPP_ROW01 0x00cc 0x0358 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_RX_EN__USDHC1_VSELECT 0x00cc 0x0358 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x00d0 0x035c 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DCE_CTS 0x00d0 0x035c 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__UART5_DTE_RTS 0x00d0 0x035c 0x0640 1 4 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__CSI_DATA19 0x00d0 0x035c 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x00d0 0x035c 0x0588 4 1 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x00d0 0x035c 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__KPP_COL01 0x00d0 0x035c 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA0__USDHC2_VSELECT 0x00d0 0x035c 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x00d4 0x0360 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DCE_CTS 0x00d4 0x0360 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__UART6_DTE_RTS 0x00d4 0x0360 0x0648 1 2 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__PWM5_OUT 0x00d4 0x0360 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__CSI_DATA20 0x00d4 0x0360 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__ENET2_MDIO 0x00d4 0x0360 0x0580 4 1 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x00d4 0x0360 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__KPP_ROW02 0x00d4 0x0360 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_TX_DATA1__WDOG1_WDOG_RST_B_DEB 0x00d4 0x0360 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x00d8 0x0364 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__UART6_DCE_RTS 0x00d8 0x0364 0x0648 1 3 |
||||
#define MX6UL_PAD_ENET1_TX_EN__UART6_DTE_CTS 0x00d8 0x0364 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00d8 0x0364 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__CSI_DATA21 0x00d8 0x0364 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__ENET2_MDC 0x00d8 0x0364 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x00d8 0x0364 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__KPP_COL02 0x00d8 0x0364 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_TX_EN__WDOG2_WDOG_RST_B_DEB 0x00d8 0x0364 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x00dc 0x0368 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__UART7_DCE_CTS 0x00dc 0x0368 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__UART7_DTE_RTS 0x00dc 0x0368 0x0650 1 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00dc 0x0368 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__CSI_DATA22 0x00dc 0x0368 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x00dc 0x0368 0x0574 4 2 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__GPIO2_IO06 0x00dc 0x0368 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__KPP_ROW03 0x00dc 0x0368 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_TX_CLK__GPT1_CLK 0x00dc 0x0368 0x0594 8 1 |
||||
#define MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x00e0 0x036c 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET1_RX_ER__UART7_DCE_RTS 0x00e0 0x036c 0x0650 1 1 |
||||
#define MX6UL_PAD_ENET1_RX_ER__UART7_DTE_CTS 0x00e0 0x036c 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET1_RX_ER__PWM8_OUT 0x00e0 0x036c 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET1_RX_ER__CSI_DATA23 0x00e0 0x036c 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET1_RX_ER__EIM_CRE 0x00e0 0x036c 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x00e0 0x036c 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET1_RX_ER__KPP_COL03 0x00e0 0x036c 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET1_RX_ER__GPT1_CAPTURE2 0x00e0 0x036c 0x0590 8 1 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x00e4 0x0370 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DCE_TX 0x00e4 0x0370 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__UART6_DTE_RX 0x00e4 0x0370 0x064c 1 1 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__SIM1_PORT0_TRXD 0x00e4 0x0370 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__I2C3_SCL 0x00e4 0x0370 0x05b4 3 1 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x00e4 0x0370 0x0578 4 1 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x00e4 0x0370 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x00e4 0x0370 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__USB_OTG1_PWR 0x00e4 0x0370 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x00e8 0x0374 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DCE_RX 0x00e8 0x0374 0x064c 1 2 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__UART6_DTE_TX 0x00e8 0x0374 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__SIM1_PORT0_cLK 0x00e8 0x0374 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__I2C3_SDA 0x00e8 0x0374 0x05b8 3 1 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x00e8 0x0374 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x00e8 0x0374 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x00e8 0x0374 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__USB_OTG1_OC 0x00e8 0x0374 0x0664 8 1 |
||||
#define MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x00ec 0x0378 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__UART7_DCE_TX 0x00ec 0x0378 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__UART7_DTE_RX 0x00ec 0x0378 0x0654 1 0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__SIM1_PORT0_RST_B 0x00ec 0x0378 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__I2C4_SCL 0x00ec 0x0378 0x05bc 3 1 |
||||
#define MX6UL_PAD_ENET2_RX_EN__EIM_ADDR26 0x00ec 0x0378 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x00ec 0x0378 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x00ec 0x0378 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M 0x00ec 0x0378 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x00f0 0x037c 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DCE_RX 0x00f0 0x037c 0x0654 1 1 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__UART7_DTE_TX 0x00f0 0x037c 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__SIM1_PORT0_SVEN 0x00f0 0x037c 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__I2C4_SDA 0x00f0 0x037c 0x05c0 3 1 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__EIM_EB_B02 0x00f0 0x037c 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x00f0 0x037c 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x00f0 0x037c 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x00f4 0x0380 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x00f4 0x0380 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__UART8_DTE_RX 0x00f4 0x0380 0x065c 1 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__SIM2_PORT0_TRXD 0x00f4 0x0380 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x00f4 0x0380 0x0564 3 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__EIM_EB_B03 0x00f4 0x0380 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x00f4 0x0380 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x00f4 0x0380 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__USB_OTG2_PWR 0x00f4 0x0380 0x0000 8 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x00f8 0x0384 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x00f8 0x0384 0x065c 1 1 |
||||
#define MX6UL_PAD_ENET2_TX_EN__UART8_DTE_TX 0x00f8 0x0384 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__SIM2_PORT0_cLK 0x00f8 0x0384 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x00f8 0x0384 0x056c 3 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__EIM_ACLK_FREERUN 0x00f8 0x0384 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x00f8 0x0384 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x00f8 0x0384 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__USB_OTG2_OC 0x00f8 0x0384 0x0660 8 1 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00fc 0x0388 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x00fc 0x0388 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__UART8_DTE_RTS 0x00fc 0x0388 0x0658 1 0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__SIM2_PORT0_RST_B 0x00fc 0x0388 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x00fc 0x0388 0x0568 3 0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00fc 0x0388 0x057c 4 2 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__GPIO2_IO14 0x00fc 0x0388 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x00fc 0x0388 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__ANATOP_OTG2_ID 0x00fc 0x0388 0x04bc 8 1 |
||||
#define MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0100 0x038c 0x0000 0 0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x0100 0x038c 0x0658 1 1 |
||||
#define MX6UL_PAD_ENET2_RX_ER__UART8_DTE_CTS 0x0100 0x038c 0x0000 1 0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__SIM2_PORT0_SVEN 0x0100 0x038c 0x0000 2 0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__ECSPI4_SS0 0x0100 0x038c 0x0000 3 0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__EIM_ADDR25 0x0100 0x038c 0x0000 4 0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0100 0x038c 0x0000 5 0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x0100 0x038c 0x0000 6 0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__WDOG1_WDOG_ANY 0x0100 0x038c 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x0104 0x0390 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_CLK__LCDIF_WR_RWN 0x0104 0x0390 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_CLK__UART4_DCE_TX 0x0104 0x0390 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_CLK__UART4_DTE_RX 0x0104 0x0390 0x063c 2 2 |
||||
#define MX6UL_PAD_LCD_CLK__SAI3_MCLK 0x0104 0x0390 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_CLK__EIM_CS2_B 0x0104 0x0390 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_CLK__GPIO3_IO00 0x0104 0x0390 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_CLK__WDOG1_WDOG_RST_B_DEB 0x0104 0x0390 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x0108 0x0394 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_ENABLE__LCDIF_RD_E 0x0108 0x0394 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX 0x0108 0x0394 0x063c 2 3 |
||||
#define MX6UL_PAD_LCD_ENABLE__UART4_DTE_TX 0x0108 0x0394 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_ENABLE__SAI3_TX_SYNC 0x0108 0x0394 0x060c 3 0 |
||||
#define MX6UL_PAD_LCD_ENABLE__EIM_CS3_B 0x0108 0x0394 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_ENABLE__GPIO3_IO01 0x0108 0x0394 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_ENABLE__ECSPI2_RDY 0x0108 0x0394 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x010c 0x0398 0x05dc 0 0 |
||||
#define MX6UL_PAD_LCD_HSYNC__LCDIF_RS 0x010c 0x0398 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_HSYNC__UART4_DCE_CTS 0x010c 0x0398 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_HSYNC__UART4_DTE_RTS 0x010c 0x0398 0x0638 2 2 |
||||
#define MX6UL_PAD_LCD_HSYNC__SAI3_TX_BCLK 0x010c 0x0398 0x0608 3 0 |
||||
#define MX6UL_PAD_LCD_HSYNC__WDOG3_WDOG_RST_B_DEB 0x010c 0x0398 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_HSYNC__GPIO3_IO02 0x010c 0x0398 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_HSYNC__ECSPI2_SS1 0x010c 0x0398 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x0110 0x039c 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_VSYNC__LCDIF_BUSY 0x0110 0x039c 0x05dc 1 1 |
||||
#define MX6UL_PAD_LCD_VSYNC__UART4_DCE_RTS 0x0110 0x039c 0x0638 2 3 |
||||
#define MX6UL_PAD_LCD_VSYNC__UART4_DTE_CTS 0x0110 0x039c 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_VSYNC__SAI3_RX_DATA 0x0110 0x039c 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_VSYNC__WDOG2_WDOG_B 0x0110 0x039c 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_VSYNC__GPIO3_IO03 0x0110 0x039c 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_VSYNC__ECSPI2_SS2 0x0110 0x039c 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_RESET__LCDIF_RESET 0x0114 0x03a0 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_RESET__LCDIF_CS 0x0114 0x03a0 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_RESET__CA7_MX6UL_EVENTI 0x0114 0x03a0 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_RESET__SAI3_TX_DATA 0x0114 0x03a0 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x0114 0x03a0 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0114 0x03a0 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_RESET__ECSPI2_SS3 0x0114 0x03a0 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x0118 0x03a4 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA00__PWM1_OUT 0x0118 0x03a4 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA00__ENET1_1588_EVENT2_IN 0x0118 0x03a4 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA00__I2C3_SDA 0x0118 0x03a4 0x05b8 4 2 |
||||
#define MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0118 0x03a4 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA00__SRC_BT_CFG00 0x0118 0x03a4 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA00__SAI1_MCLK 0x0118 0x03a4 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x011c 0x03a8 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA01__PWM2_OUT 0x011c 0x03a8 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA01__ENET1_1588_EVENT2_OUT 0x011c 0x03a8 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA01__I2C3_SCL 0x011c 0x03a8 0x05b4 4 2 |
||||
#define MX6UL_PAD_LCD_DATA01__GPIO3_IO06 0x011c 0x03a8 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA01__SRC_BT_CFG01 0x011c 0x03a8 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA01__SAI1_TX_SYNC 0x011c 0x03a8 0x05ec 8 0 |
||||
#define MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x0120 0x03ac 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA02__PWM3_OUT 0x0120 0x03ac 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA02__ENET1_1588_EVENT3_IN 0x0120 0x03ac 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA02__I2C4_SDA 0x0120 0x03ac 0x05c0 4 2 |
||||
#define MX6UL_PAD_LCD_DATA02__GPIO3_IO07 0x0120 0x03ac 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA02__SRC_BT_CFG02 0x0120 0x03ac 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA02__SAI1_TX_BCLK 0x0120 0x03ac 0x05e8 8 0 |
||||
#define MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x0124 0x03b0 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA03__PWM4_OUT 0x0124 0x03b0 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA03__ENET1_1588_EVENT3_OUT 0x0124 0x03b0 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA03__I2C4_SCL 0x0124 0x03b0 0x05bc 4 2 |
||||
#define MX6UL_PAD_LCD_DATA03__GPIO3_IO08 0x0124 0x03b0 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA03__SRC_BT_CFG03 0x0124 0x03b0 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA03__SAI1_RX_DATA 0x0124 0x03b0 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x0128 0x03b4 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA04__UART8_DCE_CTS 0x0128 0x03b4 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA04__UART8_DTE_RTS 0x0128 0x03b4 0x0658 1 2 |
||||
#define MX6UL_PAD_LCD_DATA04__ENET2_1588_EVENT2_IN 0x0128 0x03b4 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA04__SPDIF_SR_CLK 0x0128 0x03b4 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA04__GPIO3_IO09 0x0128 0x03b4 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA04__SRC_BT_CFG04 0x0128 0x03b4 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA04__SAI1_TX_DATA 0x0128 0x03b4 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x012c 0x03b8 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA05__UART8_DCE_RTS 0x012c 0x03b8 0x0658 1 3 |
||||
#define MX6UL_PAD_LCD_DATA05__UART8_DTE_CTS 0x012c 0x03b8 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA05__ENET2_1588_EVENT2_OUT 0x012c 0x03b8 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA05__SPDIF_OUT 0x012c 0x03b8 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA05__GPIO3_IO10 0x012c 0x03b8 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA05__SRC_BT_CFG05 0x012c 0x03b8 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA05__ECSPI1_SS1 0x012c 0x03b8 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x0130 0x03bc 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA06__UART7_DCE_CTS 0x0130 0x03bc 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA06__UART7_DTE_RTS 0x0130 0x03bc 0x0650 1 2 |
||||
#define MX6UL_PAD_LCD_DATA06__ENET2_1588_EVENT3_IN 0x0130 0x03bc 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA06__SPDIF_LOCK 0x0130 0x03bc 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA06__GPIO3_IO11 0x0130 0x03bc 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA06__SRC_BT_CFG06 0x0130 0x03bc 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA06__ECSPI1_SS2 0x0130 0x03bc 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x0134 0x03c0 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA07__UART7_DCE_RTS 0x0134 0x03c0 0x0650 1 3 |
||||
#define MX6UL_PAD_LCD_DATA07__UART7_DTE_CTS 0x0134 0x03c0 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA07__ENET2_1588_EVENT3_OUT 0x0134 0x03c0 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA07__SPDIF_EXT_CLK 0x0134 0x03c0 0x061c 4 0 |
||||
#define MX6UL_PAD_LCD_DATA07__GPIO3_IO12 0x0134 0x03c0 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA07__SRC_BT_CFG07 0x0134 0x03c0 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA07__ECSPI1_SS3 0x0134 0x03c0 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x0138 0x03c4 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA08__SPDIF_IN 0x0138 0x03c4 0x0618 1 2 |
||||
#define MX6UL_PAD_LCD_DATA08__CSI_DATA16 0x0138 0x03c4 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA08__EIM_DATA00 0x0138 0x03c4 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA08__GPIO3_IO13 0x0138 0x03c4 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA08__SRC_BT_CFG08 0x0138 0x03c4 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX 0x0138 0x03c4 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x013c 0x03c8 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA09__SAI3_MCLK 0x013c 0x03c8 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA09__CSI_DATA17 0x013c 0x03c8 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA09__EIM_DATA01 0x013c 0x03c8 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA09__GPIO3_IO14 0x013c 0x03c8 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA09__SRC_BT_CFG09 0x013c 0x03c8 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX 0x013c 0x03c8 0x0584 8 2 |
||||
#define MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x0140 0x03cc 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA10__SAI3_RX_SYNC 0x0140 0x03cc 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA10__CSI_DATA18 0x0140 0x03cc 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA10__EIM_DATA02 0x0140 0x03cc 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA10__GPIO3_IO15 0x0140 0x03cc 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA10__SRC_BT_CFG10 0x0140 0x03cc 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA10__FLEXCAN2_TX 0x0140 0x03cc 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x0144 0x03d0 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA11__SAI3_RX_BCLK 0x0144 0x03d0 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA11__CSI_DATA19 0x0144 0x03d0 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA11__EIM_DATA03 0x0144 0x03d0 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA11__GPIO3_IO16 0x0144 0x03d0 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA11__SRC_BT_CFG11 0x0144 0x03d0 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA11__FLEXCAN2_RX 0x0144 0x03d0 0x0588 8 2 |
||||
#define MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x0148 0x03d4 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA12__SAI3_TX_SYNC 0x0148 0x03d4 0x060c 1 1 |
||||
#define MX6UL_PAD_LCD_DATA12__CSI_DATA20 0x0148 0x03d4 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA12__EIM_DATA04 0x0148 0x03d4 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA12__GPIO3_IO17 0x0148 0x03d4 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA12__SRC_BT_CFG12 0x0148 0x03d4 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA12__ECSPI1_RDY 0x0148 0x03d4 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x014c 0x03d8 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA13__SAI3_TX_BCLK 0x014c 0x03d8 0x0608 1 1 |
||||
#define MX6UL_PAD_LCD_DATA13__CSI_DATA21 0x014c 0x03d8 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA13__EIM_DATA05 0x014c 0x03d8 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA13__GPIO3_IO18 0x014c 0x03d8 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA13__SRC_BT_CFG13 0x014c 0x03d8 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA13__USDHC2_RESET_B 0x014c 0x03d8 0x0000 8 0 |
||||
#define MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x0150 0x03dc 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA14__SAI3_RX_DATA 0x0150 0x03dc 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA14__CSI_DATA22 0x0150 0x03dc 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA14__EIM_DATA06 0x0150 0x03dc 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA14__GPIO3_IO19 0x0150 0x03dc 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA14__SRC_BT_CFG14 0x0150 0x03dc 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA14__USDHC2_DATA4 0x0150 0x03dc 0x068c 8 0 |
||||
#define MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x0154 0x03e0 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA15__SAI3_TX_DATA 0x0154 0x03e0 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA15__CSI_DATA23 0x0154 0x03e0 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA15__EIM_DATA07 0x0154 0x03e0 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA15__GPIO3_IO20 0x0154 0x03e0 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA15__SRC_BT_CFG15 0x0154 0x03e0 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA15__USDHC2_DATA5 0x0154 0x03e0 0x0690 8 0 |
||||
#define MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x0158 0x03e4 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA16__UART7_DCE_TX 0x0158 0x03e4 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA16__UART7_DTE_RX 0x0158 0x03e4 0x0654 1 2 |
||||
#define MX6UL_PAD_LCD_DATA16__CSI_DATA01 0x0158 0x03e4 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA16__EIM_DATA08 0x0158 0x03e4 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA16__GPIO3_IO21 0x0158 0x03e4 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA16__SRC_BT_CFG24 0x0158 0x03e4 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA16__USDHC2_DATA6 0x0158 0x03e4 0x0694 8 0 |
||||
#define MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x015c 0x03e8 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA17__UART7_DCE_RX 0x015c 0x03e8 0x0654 1 3 |
||||
#define MX6UL_PAD_LCD_DATA17__UART7_DTE_TX 0x015c 0x03e8 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA17__CSI_DATA00 0x015c 0x03e8 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA17__EIM_DATA09 0x015c 0x03e8 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA17__GPIO3_IO22 0x015c 0x03e8 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA17__SRC_BT_CFG25 0x015c 0x03e8 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA17__USDHC2_DATA7 0x015c 0x03e8 0x0698 8 0 |
||||
#define MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x0160 0x03ec 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA18__PWM5_OUT 0x0160 0x03ec 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA18__CA7_MX6UL_EVENTO 0x0160 0x03ec 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_DATA18__CSI_DATA10 0x0160 0x03ec 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA18__EIM_DATA10 0x0160 0x03ec 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x0160 0x03ec 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA18__SRC_BT_CFG26 0x0160 0x03ec 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x0160 0x03ec 0x0678 8 1 |
||||
#define MX6UL_PAD_LCD_DATA19__EIM_DATA11 0x0164 0x03f0 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x0164 0x03f0 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA19__SRC_BT_CFG27 0x0164 0x03f0 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x0164 0x03f0 0x0670 8 1 |
||||
#define MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x0164 0x03f0 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA19__PWM6_OUT 0x0164 0x03f0 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA19__WDOG1_WDOG_ANY 0x0164 0x03f0 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_DATA19__CSI_DATA11 0x0164 0x03f0 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA20__EIM_DATA12 0x0168 0x03f4 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA20__GPIO3_IO25 0x0168 0x03f4 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA20__SRC_BT_CFG28 0x0168 0x03f4 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x0168 0x03f4 0x067c 8 1 |
||||
#define MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x0168 0x03f4 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA20__UART8_DCE_TX 0x0168 0x03f4 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA20__UART8_DTE_RX 0x0168 0x03f4 0x065c 1 2 |
||||
#define MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x0168 0x03f4 0x0534 2 0 |
||||
#define MX6UL_PAD_LCD_DATA20__CSI_DATA12 0x0168 0x03f4 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x016c 0x03f8 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA21__UART8_DCE_RX 0x016c 0x03f8 0x065c 1 3 |
||||
#define MX6UL_PAD_LCD_DATA21__UART8_DTE_TX 0x016c 0x03f8 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA21__ECSPI1_SS0 0x016c 0x03f8 0x0000 2 0 |
||||
#define MX6UL_PAD_LCD_DATA21__CSI_DATA13 0x016c 0x03f8 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA21__EIM_DATA13 0x016c 0x03f8 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x016c 0x03f8 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA21__SRC_BT_CFG29 0x016c 0x03f8 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x016c 0x03f8 0x0680 8 1 |
||||
#define MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x0170 0x03fc 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA22__MQS_RIGHT 0x0170 0x03fc 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x0170 0x03fc 0x053c 2 0 |
||||
#define MX6UL_PAD_LCD_DATA22__CSI_DATA14 0x0170 0x03fc 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA22__EIM_DATA14 0x0170 0x03fc 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA22__GPIO3_IO27 0x0170 0x03fc 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA22__SRC_BT_CFG30 0x0170 0x03fc 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x0170 0x03fc 0x0684 8 0 |
||||
#define MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x0174 0x0400 0x0000 0 0 |
||||
#define MX6UL_PAD_LCD_DATA23__MQS_LEFT 0x0174 0x0400 0x0000 1 0 |
||||
#define MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x0174 0x0400 0x0538 2 0 |
||||
#define MX6UL_PAD_LCD_DATA23__CSI_DATA15 0x0174 0x0400 0x0000 3 0 |
||||
#define MX6UL_PAD_LCD_DATA23__EIM_DATA15 0x0174 0x0400 0x0000 4 0 |
||||
#define MX6UL_PAD_LCD_DATA23__GPIO3_IO28 0x0174 0x0400 0x0000 5 0 |
||||
#define MX6UL_PAD_LCD_DATA23__SRC_BT_CFG31 0x0174 0x0400 0x0000 6 0 |
||||
#define MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x0174 0x0400 0x0688 8 1 |
||||
#define MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0178 0x0404 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x0178 0x0404 0x0670 1 2 |
||||
#define MX6UL_PAD_NAND_RE_B__QSPI_B_SCLK 0x0178 0x0404 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_RE_B__KPP_ROW00 0x0178 0x0404 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_RE_B__EIM_EB_B00 0x0178 0x0404 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0178 0x0404 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_RE_B__ECSPI3_SS2 0x0178 0x0404 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x017c 0x0408 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x017c 0x0408 0x0678 1 2 |
||||
#define MX6UL_PAD_NAND_WE_B__QSPI_B_SS0_B 0x017c 0x0408 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_WE_B__KPP_COL00 0x017c 0x0408 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_WE_B__EIM_EB_B01 0x017c 0x0408 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x017c 0x0408 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_WE_B__ECSPI3_SS3 0x017c 0x0408 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0180 0x040c 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x0180 0x040c 0x067c 1 2 |
||||
#define MX6UL_PAD_NAND_DATA00__QSPI_B_SS1_B 0x0180 0x040c 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA00__KPP_ROW01 0x0180 0x040c 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_DATA00__EIM_AD08 0x0180 0x040c 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x0180 0x040c 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA00__ECSPI4_RDY 0x0180 0x040c 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0184 0x0410 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x0184 0x0410 0x0680 1 2 |
||||
#define MX6UL_PAD_NAND_DATA01__QSPI_B_DQS 0x0184 0x0410 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA01__KPP_COL01 0x0184 0x0410 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_DATA01__EIM_AD09 0x0184 0x0410 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x0184 0x0410 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA01__ECSPI4_SS1 0x0184 0x0410 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0188 0x0414 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x0188 0x0414 0x0684 1 1 |
||||
#define MX6UL_PAD_NAND_DATA02__QSPI_B_DATA00 0x0188 0x0414 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA02__KPP_ROW02 0x0188 0x0414 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_DATA02__EIM_AD10 0x0188 0x0414 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA02__GPIO4_IO04 0x0188 0x0414 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA02__ECSPI4_SS2 0x0188 0x0414 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x018c 0x0418 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x018c 0x0418 0x0688 1 2 |
||||
#define MX6UL_PAD_NAND_DATA03__QSPI_B_DATA01 0x018c 0x0418 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA03__KPP_COL02 0x018c 0x0418 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_DATA03__EIM_AD11 0x018c 0x0418 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA03__GPIO4_IO05 0x018c 0x0418 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA03__ECSPI4_SS3 0x018c 0x0418 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0190 0x041c 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x0190 0x041c 0x068c 1 1 |
||||
#define MX6UL_PAD_NAND_DATA04__QSPI_B_DATA02 0x0190 0x041c 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x0190 0x041c 0x0564 3 1 |
||||
#define MX6UL_PAD_NAND_DATA04__EIM_AD12 0x0190 0x041c 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA04__GPIO4_IO06 0x0190 0x041c 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x0190 0x041c 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA04__UART2_DTE_RX 0x0190 0x041c 0x062c 8 2 |
||||
#define MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0194 0x0420 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x0194 0x0420 0x0690 1 1 |
||||
#define MX6UL_PAD_NAND_DATA05__QSPI_B_DATA03 0x0194 0x0420 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x0194 0x0420 0x056c 3 1 |
||||
#define MX6UL_PAD_NAND_DATA05__EIM_AD13 0x0194 0x0420 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA05__GPIO4_IO07 0x0194 0x0420 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x0194 0x0420 0x062c 8 3 |
||||
#define MX6UL_PAD_NAND_DATA05__UART2_DTE_TX 0x0194 0x0420 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0198 0x0424 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x0198 0x0424 0x0694 1 1 |
||||
#define MX6UL_PAD_NAND_DATA06__SAI2_RX_BCLK 0x0198 0x0424 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x0198 0x0424 0x0568 3 1 |
||||
#define MX6UL_PAD_NAND_DATA06__EIM_AD14 0x0198 0x0424 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA06__GPIO4_IO08 0x0198 0x0424 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x0198 0x0424 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DATA06__UART2_DTE_RTS 0x0198 0x0424 0x0628 8 4 |
||||
#define MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x019c 0x0428 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x019c 0x0428 0x0698 1 1 |
||||
#define MX6UL_PAD_NAND_DATA07__QSPI_A_SS1_B 0x019c 0x0428 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DATA07__ECSPI4_SS0 0x019c 0x0428 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_DATA07__EIM_AD15 0x019c 0x0428 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x019c 0x0428 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x019c 0x0428 0x0628 8 5 |
||||
#define MX6UL_PAD_NAND_DATA07__UART2_DTE_CTS 0x019c 0x0428 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x01a0 0x042c 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x01a0 0x042c 0x0000 1 0 |
||||
#define MX6UL_PAD_NAND_ALE__QSPI_A_DQS 0x01a0 0x042c 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_ALE__PWM3_OUT 0x01a0 0x042c 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_ALE__EIM_ADDR17 0x01a0 0x042c 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_ALE__GPIO4_IO10 0x01a0 0x042c 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_ALE__ECSPI3_SS1 0x01a0 0x042c 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x01a4 0x0430 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_WP_B__USDHC1_RESET_B 0x01a4 0x0430 0x0000 1 0 |
||||
#define MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x01a4 0x0430 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x01a4 0x0430 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_WP_B__EIM_BCLK 0x01a4 0x0430 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_WP_B__GPIO4_IO11 0x01a4 0x0430 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_WP_B__ECSPI3_RDY 0x01a4 0x0430 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x01a8 0x0434 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x01a8 0x0434 0x0000 1 0 |
||||
#define MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x01a8 0x0434 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_READY_B__ECSPI3_SS0 0x01a8 0x0434 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_READY_B__EIM_CS1_B 0x01a8 0x0434 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_READY_B__GPIO4_IO12 0x01a8 0x0434 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_READY_B__UART3_DCE_TX 0x01a8 0x0434 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_READY_B__UART3_DTE_RX 0x01a8 0x0434 0x0634 8 2 |
||||
#define MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x01ac 0x0438 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x01ac 0x0438 0x0000 1 0 |
||||
#define MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x01ac 0x0438 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_CE0_B__ECSPI3_SCLK 0x01ac 0x0438 0x0554 3 1 |
||||
#define MX6UL_PAD_NAND_CE0_B__EIM_DTACK_B 0x01ac 0x0438 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_CE0_B__GPIO4_IO13 0x01ac 0x0438 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_CE0_B__UART3_DCE_RX 0x01ac 0x0438 0x0634 8 3 |
||||
#define MX6UL_PAD_NAND_CE0_B__UART3_DTE_TX 0x01ac 0x0438 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x01b0 0x043c 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x01b0 0x043c 0x0000 1 0 |
||||
#define MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x01b0 0x043c 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_CE1_B__ECSPI3_MOSI 0x01b0 0x043c 0x055c 3 1 |
||||
#define MX6UL_PAD_NAND_CE1_B__EIM_ADDR18 0x01b0 0x043c 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x01b0 0x043c 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_CE1_B__UART3_DCE_CTS 0x01b0 0x043c 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_CE1_B__UART3_DTE_RTS 0x01b0 0x043c 0x0630 8 2 |
||||
#define MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x01b4 0x0440 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x01b4 0x0440 0x0000 1 0 |
||||
#define MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x01b4 0x0440 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_CLE__ECSPI3_MISO 0x01b4 0x0440 0x0558 3 1 |
||||
#define MX6UL_PAD_NAND_CLE__EIM_ADDR16 0x01b4 0x0440 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_CLE__GPIO4_IO15 0x01b4 0x0440 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_CLE__UART3_DCE_RTS 0x01b4 0x0440 0x0630 8 3 |
||||
#define MX6UL_PAD_NAND_CLE__UART3_DTE_CTS 0x01b4 0x0440 0x0000 8 0 |
||||
#define MX6UL_PAD_NAND_DQS__RAWNAND_DQS 0x01b8 0x0444 0x0000 0 0 |
||||
#define MX6UL_PAD_NAND_DQS__CSI_FIELD 0x01b8 0x0444 0x0530 1 1 |
||||
#define MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x01b8 0x0444 0x0000 2 0 |
||||
#define MX6UL_PAD_NAND_DQS__PWM5_OUT 0x01b8 0x0444 0x0000 3 0 |
||||
#define MX6UL_PAD_NAND_DQS__EIM_WAIT 0x01b8 0x0444 0x0000 4 0 |
||||
#define MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x01b8 0x0444 0x0000 5 0 |
||||
#define MX6UL_PAD_NAND_DQS__SDMA_EXT_EVENT01 0x01b8 0x0444 0x0000 6 0 |
||||
#define MX6UL_PAD_NAND_DQS__SPDIF_EXT_CLK 0x01b8 0x0444 0x061c 8 1 |
||||
#define MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x01bc 0x0448 0x0000 0 0 |
||||
#define MX6UL_PAD_SD1_CMD__GPT2_COMPARE1 0x01bc 0x0448 0x0000 1 0 |
||||
#define MX6UL_PAD_SD1_CMD__SAI2_RX_SYNC 0x01bc 0x0448 0x0000 2 0 |
||||
#define MX6UL_PAD_SD1_CMD__SPDIF_OUT 0x01bc 0x0448 0x0000 3 0 |
||||
#define MX6UL_PAD_SD1_CMD__EIM_ADDR19 0x01bc 0x0448 0x0000 4 0 |
||||
#define MX6UL_PAD_SD1_CMD__GPIO2_IO16 0x01bc 0x0448 0x0000 5 0 |
||||
#define MX6UL_PAD_SD1_CMD__SDMA_EXT_EVENT00 0x01bc 0x0448 0x0000 6 0 |
||||
#define MX6UL_PAD_SD1_CMD__USB_OTG1_PWR 0x01bc 0x0448 0x0000 8 0 |
||||
#define MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x01c0 0x044c 0x0000 0 0 |
||||
#define MX6UL_PAD_SD1_CLK__GPT2_COMPARE2 0x01c0 0x044c 0x0000 1 0 |
||||
#define MX6UL_PAD_SD1_CLK__SAI2_MCLK 0x01c0 0x044c 0x0000 2 0 |
||||
#define MX6UL_PAD_SD1_CLK__SPDIF_IN 0x01c0 0x044c 0x0618 3 3 |
||||
#define MX6UL_PAD_SD1_CLK__EIM_ADDR20 0x01c0 0x044c 0x0000 4 0 |
||||
#define MX6UL_PAD_SD1_CLK__GPIO2_IO17 0x01c0 0x044c 0x0000 5 0 |
||||
#define MX6UL_PAD_SD1_CLK__USB_OTG1_OC 0x01c0 0x044c 0x0664 8 2 |
||||
#define MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x01c4 0x0450 0x0000 0 0 |
||||
#define MX6UL_PAD_SD1_DATA0__GPT2_COMPARE3 0x01c4 0x0450 0x0000 1 0 |
||||
#define MX6UL_PAD_SD1_DATA0__SAI2_TX_SYNC 0x01c4 0x0450 0x05fc 2 1 |
||||
#define MX6UL_PAD_SD1_DATA0__FLEXCAN1_TX 0x01c4 0x0450 0x0000 3 0 |
||||
#define MX6UL_PAD_SD1_DATA0__EIM_ADDR21 0x01c4 0x0450 0x0000 4 0 |
||||
#define MX6UL_PAD_SD1_DATA0__GPIO2_IO18 0x01c4 0x0450 0x0000 5 0 |
||||
#define MX6UL_PAD_SD1_DATA0__ANATOP_OTG1_ID 0x01c4 0x0450 0x04b8 8 2 |
||||
#define MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x01c8 0x0454 0x0000 0 0 |
||||
#define MX6UL_PAD_SD1_DATA1__GPT2_CLK 0x01c8 0x0454 0x05a0 1 1 |
||||
#define MX6UL_PAD_SD1_DATA1__SAI2_TX_BCLK 0x01c8 0x0454 0x05f8 2 1 |
||||
#define MX6UL_PAD_SD1_DATA1__FLEXCAN1_RX 0x01c8 0x0454 0x0584 3 3 |
||||
#define MX6UL_PAD_SD1_DATA1__EIM_ADDR22 0x01c8 0x0454 0x0000 4 0 |
||||
#define MX6UL_PAD_SD1_DATA1__GPIO2_IO19 0x01c8 0x0454 0x0000 5 0 |
||||
#define MX6UL_PAD_SD1_DATA1__USB_OTG2_PWR 0x01c8 0x0454 0x0000 8 0 |
||||
#define MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x01cc 0x0458 0x0000 0 0 |
||||
#define MX6UL_PAD_SD1_DATA2__GPT2_CAPTURE1 0x01cc 0x0458 0x0598 1 1 |
||||
#define MX6UL_PAD_SD1_DATA2__SAI2_RX_DATA 0x01cc 0x0458 0x05f4 2 1 |
||||
#define MX6UL_PAD_SD1_DATA2__FLEXCAN2_TX 0x01cc 0x0458 0x0000 3 0 |
||||
#define MX6UL_PAD_SD1_DATA2__EIM_ADDR23 0x01cc 0x0458 0x0000 4 0 |
||||
#define MX6UL_PAD_SD1_DATA2__GPIO2_IO20 0x01cc 0x0458 0x0000 5 0 |
||||
#define MX6UL_PAD_SD1_DATA2__CCM_CLKO1 0x01cc 0x0458 0x0000 6 0 |
||||
#define MX6UL_PAD_SD1_DATA2__USB_OTG2_OC 0x01cc 0x0458 0x0660 8 2 |
||||
#define MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x01d0 0x045c 0x0000 0 0 |
||||
#define MX6UL_PAD_SD1_DATA3__GPT2_CAPTURE2 0x01d0 0x045c 0x059c 1 1 |
||||
#define MX6UL_PAD_SD1_DATA3__SAI2_TX_DATA 0x01d0 0x045c 0x0000 2 0 |
||||
#define MX6UL_PAD_SD1_DATA3__FLEXCAN2_RX 0x01d0 0x045c 0x0588 3 3 |
||||
#define MX6UL_PAD_SD1_DATA3__EIM_ADDR24 0x01d0 0x045c 0x0000 4 0 |
||||
#define MX6UL_PAD_SD1_DATA3__GPIO2_IO21 0x01d0 0x045c 0x0000 5 0 |
||||
#define MX6UL_PAD_SD1_DATA3__CCM_CLKO2 0x01d0 0x045c 0x0000 6 0 |
||||
#define MX6UL_PAD_SD1_DATA3__ANATOP_OTG2_ID 0x01d0 0x045c 0x04bc 8 2 |
||||
#define MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x01d4 0x0460 0x0000 0 0 |
||||
#define MX6UL_PAD_CSI_MCLK__USDHC2_CD_B 0x01d4 0x0460 0x0674 1 0 |
||||
#define MX6UL_PAD_CSI_MCLK__RAWNAND_CE2_B 0x01d4 0x0460 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x01d4 0x0460 0x05a8 3 0 |
||||
#define MX6UL_PAD_CSI_MCLK__EIM_CS0_B 0x01d4 0x0460 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x01d4 0x0460 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_MCLK__SNVS_HP_VIO_5_CTL 0x01d4 0x0460 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x01d4 0x0460 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_MCLK__UART6_DTE_RX 0x01d4 0x0460 0x064c 8 0 |
||||
#define MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x01d8 0x0464 0x0528 0 1 |
||||
#define MX6UL_PAD_CSI_PIXCLK__USDHC2_WP 0x01d8 0x0464 0x069c 1 2 |
||||
#define MX6UL_PAD_CSI_PIXCLK__RAWNAND_CE3_B 0x01d8 0x0464 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x01d8 0x0464 0x05a4 3 2 |
||||
#define MX6UL_PAD_CSI_PIXCLK__EIM_OE 0x01d8 0x0464 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x01d8 0x0464 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_PIXCLK__SNVS_HP_VIO_5 0x01d8 0x0464 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x01d8 0x0464 0x064c 8 3 |
||||
#define MX6UL_PAD_CSI_PIXCLK__UART6_DTE_TX 0x01d8 0x0464 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x01dc 0x0468 0x052c 0 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x01dc 0x0468 0x0670 1 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__SIM1_PORT1_CLK 0x01dc 0x0468 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__I2C2_SDA 0x01dc 0x0468 0x05b0 3 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__EIM_RW 0x01dc 0x0468 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x01dc 0x0468 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__PWM7_OUT 0x01dc 0x0468 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x01dc 0x0468 0x0648 8 0 |
||||
#define MX6UL_PAD_CSI_VSYNC__UART6_DTE_CTS 0x01dc 0x0468 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x01e0 0x046c 0x0524 0 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x01e0 0x046c 0x0678 1 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__SIM1_PORT1_PD 0x01e0 0x046c 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__I2C2_SCL 0x01e0 0x046c 0x05ac 3 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__EIM_LBA_B 0x01e0 0x046c 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x01e0 0x046c 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x01e0 0x046c 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x01e0 0x046c 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_HSYNC__UART6_DTE_RTS 0x01e0 0x046c 0x0648 8 1 |
||||
#define MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x01e4 0x0470 0x04c4 0 0 |
||||
#define MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x01e4 0x0470 0x067c 1 0 |
||||
#define MX6UL_PAD_CSI_DATA00__SIM1_PORT1_RST_B 0x01e4 0x0470 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x01e4 0x0470 0x0544 3 0 |
||||
#define MX6UL_PAD_CSI_DATA00__EIM_AD00 0x01e4 0x0470 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x01e4 0x0470 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA00__SRC_INT_BOOT 0x01e4 0x0470 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x01e4 0x0470 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_DATA00__UART5_DTE_RX 0x01e4 0x0470 0x0644 8 0 |
||||
#define MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x01e8 0x0474 0x04c8 0 0 |
||||
#define MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x01e8 0x0474 0x0680 1 0 |
||||
#define MX6UL_PAD_CSI_DATA01__SIM1_PORT1_SVEN 0x01e8 0x0474 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA01__ECSPI2_SS0 0x01e8 0x0474 0x0000 3 0 |
||||
#define MX6UL_PAD_CSI_DATA01__EIM_AD01 0x01e8 0x0474 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x01e8 0x0474 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA01__SAI1_MCLK 0x01e8 0x0474 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x01e8 0x0474 0x0644 8 1 |
||||
#define MX6UL_PAD_CSI_DATA01__UART5_DTE_TX 0x01e8 0x0474 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x01ec 0x0478 0x04d8 0 1 |
||||
#define MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x01ec 0x0478 0x0684 1 2 |
||||
#define MX6UL_PAD_CSI_DATA02__SIM1_PORT1_TRXD 0x01ec 0x0478 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x01ec 0x0478 0x054c 3 1 |
||||
#define MX6UL_PAD_CSI_DATA02__EIM_AD02 0x01ec 0x0478 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x01ec 0x0478 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA02__SAI1_RX_SYNC 0x01ec 0x0478 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_DATA02__UART5_DCE_RTS 0x01ec 0x0478 0x0640 8 5 |
||||
#define MX6UL_PAD_CSI_DATA02__UART5_DTE_CTS 0x01ec 0x0478 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x01f0 0x047c 0x04cc 0 0 |
||||
#define MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x01f0 0x047c 0x0688 1 0 |
||||
#define MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0x01f0 0x047c 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x01f0 0x047c 0x0548 3 0 |
||||
#define MX6UL_PAD_CSI_DATA03__EIM_AD03 0x01f0 0x047c 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x01f0 0x047c 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA03__SAI1_RX_BCLK 0x01f0 0x047c 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_DATA03__UART5_DCE_CTS 0x01f0 0x047c 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_DATA03__UART5_DTE_RTS 0x01f0 0x047c 0x0640 8 0 |
||||
#define MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x01f4 0x0480 0x04dc 0 1 |
||||
#define MX6UL_PAD_CSI_DATA04__USDHC2_DATA4 0x01f4 0x0480 0x068c 1 2 |
||||
#define MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x01f4 0x0480 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x01f4 0x0480 0x0534 3 1 |
||||
#define MX6UL_PAD_CSI_DATA04__EIM_AD04 0x01f4 0x0480 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x01f4 0x0480 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA04__SAI1_TX_SYNC 0x01f4 0x0480 0x05ec 6 1 |
||||
#define MX6UL_PAD_CSI_DATA04__USDHC1_WP 0x01f4 0x0480 0x066c 8 2 |
||||
#define MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x01f8 0x0484 0x04e0 0 1 |
||||
#define MX6UL_PAD_CSI_DATA05__USDHC2_DATA5 0x01f8 0x0484 0x0690 1 2 |
||||
#define MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0x01f8 0x0484 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA05__ECSPI1_SS0 0x01f8 0x0484 0x0000 3 0 |
||||
#define MX6UL_PAD_CSI_DATA05__EIM_AD05 0x01f8 0x0484 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x01f8 0x0484 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA05__SAI1_TX_BCLK 0x01f8 0x0484 0x05e8 6 1 |
||||
#define MX6UL_PAD_CSI_DATA05__USDHC1_CD_B 0x01f8 0x0484 0x0668 8 2 |
||||
#define MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x01fc 0x0488 0x04e4 0 1 |
||||
#define MX6UL_PAD_CSI_DATA06__USDHC2_DATA6 0x01fc 0x0488 0x0694 1 2 |
||||
#define MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0x01fc 0x0488 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x01fc 0x0488 0x053c 3 1 |
||||
#define MX6UL_PAD_CSI_DATA06__EIM_AD06 0x01fc 0x0488 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x01fc 0x0488 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA06__SAI1_RX_DATA 0x01fc 0x0488 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_DATA06__USDHC1_RESET_B 0x01fc 0x0488 0x0000 8 0 |
||||
#define MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x0200 0x048c 0x04e8 0 1 |
||||
#define MX6UL_PAD_CSI_DATA07__USDHC2_DATA7 0x0200 0x048c 0x0698 1 2 |
||||
#define MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0x0200 0x048c 0x0000 2 0 |
||||
#define MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x0200 0x048c 0x0538 3 1 |
||||
#define MX6UL_PAD_CSI_DATA07__EIM_AD07 0x0200 0x048c 0x0000 4 0 |
||||
#define MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x0200 0x048c 0x0000 5 0 |
||||
#define MX6UL_PAD_CSI_DATA07__SAI1_TX_DATA 0x0200 0x048c 0x0000 6 0 |
||||
#define MX6UL_PAD_CSI_DATA07__USDHC1_VSELECT 0x0200 0x048c 0x0000 8 0 |
||||
|
||||
#endif /* __DTS_IMX6UL_PINFUNC_H */ |
@ -0,0 +1,527 @@ |
||||
/* |
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
|
||||
#include <dt-bindings/input/input.h> |
||||
#include "imx6ull.dtsi" |
||||
|
||||
/ { |
||||
model = "Freescale i.MX6 ULL 14x14 EVK Board"; |
||||
compatible = "fsl,imx6ull-14x14-evk", "fsl,imx6ull"; |
||||
|
||||
chosen { |
||||
stdout-path = &uart1; |
||||
}; |
||||
|
||||
memory { |
||||
reg = <0x80000000 0x20000000>; |
||||
}; |
||||
|
||||
backlight { |
||||
compatible = "pwm-backlight"; |
||||
pwms = <&pwm1 0 5000000>; |
||||
brightness-levels = <0 4 8 16 32 64 128 255>; |
||||
default-brightness-level = <6>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
regulators { |
||||
compatible = "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
reg_can_3v3: regulator@0 { |
||||
compatible = "regulator-fixed"; |
||||
reg = <0>; |
||||
regulator-name = "can-3v3"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; |
||||
}; |
||||
|
||||
reg_sd1_vmmc: regulator@1 { |
||||
compatible = "regulator-fixed"; |
||||
regulator-name = "VSD_3V3"; |
||||
regulator-min-microvolt = <3300000>; |
||||
regulator-max-microvolt = <3300000>; |
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
||||
enable-active-high; |
||||
}; |
||||
|
||||
reg_gpio_dvfs: regulator-gpio { |
||||
compatible = "regulator-gpio"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_dvfs>; |
||||
regulator-min-microvolt = <1300000>; |
||||
regulator-max-microvolt = <1400000>; |
||||
regulator-name = "gpio_dvfs"; |
||||
regulator-type = "voltage"; |
||||
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; |
||||
states = <1300000 0x1 1400000 0x0>; |
||||
}; |
||||
}; |
||||
|
||||
spi4 { |
||||
compatible = "spi-gpio"; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_spi4>; |
||||
status = "okay"; |
||||
gpio-sck = <&gpio5 11 0>; |
||||
gpio-mosi = <&gpio5 10 0>; |
||||
cs-gpios = <&gpio5 7 0>; |
||||
num-chipselects = <1>; |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
gpio_spi: gpio_spi@0 { |
||||
compatible = "fairchild,74hc595"; |
||||
gpio-controller; |
||||
oe-gpios = <&gpio5 8 0>; |
||||
#gpio-cells = <2>; |
||||
reg = <0>; |
||||
registers-number = <1>; |
||||
registers-default = /bits/ 8 <0x57>; |
||||
spi-max-frequency = <100000>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&cpu0 { |
||||
arm-supply = <®_arm>; |
||||
soc-supply = <®_soc>; |
||||
dc-supply = <®_gpio_dvfs>; |
||||
}; |
||||
|
||||
&clks { |
||||
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; |
||||
assigned-clock-rates = <786432000>; |
||||
}; |
||||
|
||||
&fec1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_enet1>; |
||||
phy-mode = "rmii"; |
||||
phy-handle = <ðphy0>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&fec2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_enet2>; |
||||
phy-mode = "rmii"; |
||||
phy-handle = <ðphy1>; |
||||
status = "okay"; |
||||
|
||||
mdio { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
|
||||
ethphy0: ethernet-phy@2 { |
||||
compatible = "ethernet-phy-ieee802.3-c22"; |
||||
reg = <2>; |
||||
}; |
||||
|
||||
ethphy1: ethernet-phy@1 { |
||||
compatible = "ethernet-phy-ieee802.3-c22"; |
||||
reg = <1>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&gpc { |
||||
fsl,cpu_pupscr_sw2iso = <0x1>; |
||||
fsl,cpu_pupscr_sw = <0x0>; |
||||
fsl,cpu_pdnscr_iso2sw = <0x1>; |
||||
fsl,cpu_pdnscr_iso = <0x1>; |
||||
fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ |
||||
}; |
||||
|
||||
&i2c1 { |
||||
clock-frequency = <100000>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_i2c1>; |
||||
status = "okay"; |
||||
|
||||
mag3110@0e { |
||||
compatible = "fsl,mag3110"; |
||||
reg = <0x0e>; |
||||
position = <2>; |
||||
}; |
||||
|
||||
fxls8471@1e { |
||||
compatible = "fsl,fxls8471"; |
||||
reg = <0x1e>; |
||||
position = <0>; |
||||
interrupt-parent = <&gpio5>; |
||||
interrupts = <0 8>; |
||||
}; |
||||
}; |
||||
|
||||
&i2c2 { |
||||
clock_frequency = <100000>; |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_i2c2>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&iomuxc { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_hog_1>; |
||||
imx6ul-evk { |
||||
pinctrl_hog_1: hoggrp-1 { |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ |
||||
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ |
||||
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_csi1: csi1grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 |
||||
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 |
||||
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 |
||||
MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 |
||||
MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 |
||||
MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 |
||||
MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 |
||||
MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 |
||||
MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 |
||||
MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 |
||||
MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 |
||||
MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_enet1: enet1grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 |
||||
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 |
||||
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 |
||||
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 |
||||
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 |
||||
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 |
||||
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 |
||||
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_enet2: enet2grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 |
||||
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 |
||||
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 |
||||
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 |
||||
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 |
||||
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 |
||||
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 |
||||
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 |
||||
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 |
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_flexcan1: flexcan1grp{ |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 |
||||
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_flexcan2: flexcan2grp{ |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 |
||||
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_i2c1: i2c1grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 |
||||
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_i2c2: i2c2grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 |
||||
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_lcdif_dat: lcdifdatgrp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 |
||||
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 |
||||
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 |
||||
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 |
||||
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 |
||||
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 |
||||
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 |
||||
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 |
||||
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 |
||||
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 |
||||
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 |
||||
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 |
||||
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 |
||||
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 |
||||
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 |
||||
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 |
||||
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 |
||||
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 |
||||
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 |
||||
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 |
||||
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 |
||||
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 |
||||
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 |
||||
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_lcdif_ctrl: lcdifctrlgrp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 |
||||
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 |
||||
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 |
||||
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_pwm1: pwm1grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_qspi: qspigrp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 |
||||
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 |
||||
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 |
||||
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 |
||||
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 |
||||
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_uart1: uart1grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 |
||||
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_uart2: uart2grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 |
||||
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 |
||||
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 |
||||
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_uart2dte: uart2dtegrp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 |
||||
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 |
||||
MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 |
||||
MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc1: usdhc1grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 |
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071 |
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_usdhc2: usdhc2grp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 |
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 |
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 |
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_wdog: wdoggrp { |
||||
fsl,pins = < |
||||
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 |
||||
>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&iomuxc_snvs { |
||||
pinctrl-names = "default_snvs"; |
||||
pinctrl-0 = <&pinctrl_hog_2>; |
||||
imx6ul-evk { |
||||
pinctrl_hog_2: hoggrp-2 { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_dvfs: dvfsgrp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_lcdif_reset: lcdifresetgrp { |
||||
fsl,pins = < |
||||
/* used for lcd reset */ |
||||
MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_spi4: spi4grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 |
||||
MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 |
||||
MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 |
||||
MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_sai2_hp_det_b: sai2_hp_det_grp { |
||||
fsl,pins = < |
||||
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 |
||||
>; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
|
||||
&lcdif { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_lcdif_dat |
||||
&pinctrl_lcdif_ctrl |
||||
&pinctrl_lcdif_reset>; |
||||
display = <&display0>; |
||||
status = "okay"; |
||||
|
||||
display0: display { |
||||
bits-per-pixel = <16>; |
||||
bus-width = <24>; |
||||
|
||||
display-timings { |
||||
native-mode = <&timing0>; |
||||
timing0: timing0 { |
||||
clock-frequency = <9200000>; |
||||
hactive = <480>; |
||||
vactive = <272>; |
||||
hfront-porch = <8>; |
||||
hback-porch = <4>; |
||||
hsync-len = <41>; |
||||
vback-porch = <2>; |
||||
vfront-porch = <4>; |
||||
vsync-len = <10>; |
||||
|
||||
hsync-active = <0>; |
||||
vsync-active = <0>; |
||||
de-active = <1>; |
||||
pixelclk-active = <0>; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
||||
|
||||
&pwm1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_pwm1>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&qspi { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_qspi>; |
||||
status = "okay"; |
||||
ddrsmp=<0>; |
||||
|
||||
flash0: n25q256a@0 { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
compatible = "micron,n25q256a"; |
||||
spi-max-frequency = <29000000>; |
||||
spi-nor,ddr-quad-read-dummy = <6>; |
||||
reg = <0>; |
||||
}; |
||||
}; |
||||
|
||||
&uart1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_uart1>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_uart2>; |
||||
fsl,uart-has-rtscts; |
||||
/* for DTE mode, add below change */ |
||||
/* fsl,dte-mode; */ |
||||
/* pinctrl-0 = <&pinctrl_uart2dte>; */ |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbotg1 { |
||||
dr_mode = "otg"; |
||||
srp-disable; |
||||
hnp-disable; |
||||
adp-disable; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbotg2 { |
||||
dr_mode = "host"; |
||||
disable-over-current; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usbphy1 { |
||||
tx-d-cal = <0x5>; |
||||
}; |
||||
|
||||
&usbphy2 { |
||||
tx-d-cal = <0x5>; |
||||
}; |
||||
|
||||
&usdhc1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_usdhc1>; |
||||
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; |
||||
keep-power-in-suspend; |
||||
enable-sdio-wakeup; |
||||
vmmc-supply = <®_sd1_vmmc>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&usdhc2 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_usdhc2>; |
||||
no-1-8-v; |
||||
non-removable; |
||||
keep-power-in-suspend; |
||||
enable-sdio-wakeup; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&wdog1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_wdog>; |
||||
fsl,wdog_b; |
||||
}; |
@ -0,0 +1,29 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef __DTS_IMX6ULL_PINFUNC_SNVS_H |
||||
#define __DTS_IMX6ULL_PINFUNC_SNVS_H |
||||
/*
|
||||
* The pin function ID is a tuple of |
||||
* <mux_reg conf_reg input_reg mux_mode input_val> |
||||
*/ |
||||
#define MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x0000 0x0044 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x0004 0x0048 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0008 0x004C 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x000C 0x0050 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0010 0x0054 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0014 0x0058 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0018 0x005C 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x001C 0x0060 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0020 0x0064 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0024 0x0068 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0028 0x006C 0x0000 0x5 0x0 |
||||
#define MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x002C 0x0070 0x0000 0x5 0x0 |
||||
|
||||
#endif /* __DTS_IMX6ULL_PINFUNC_SNVS_H */ |
||||
|
@ -0,0 +1,57 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef __DTS_IMX6ULL_PINFUNC_H |
||||
#define __DTS_IMX6ULL_PINFUNC_H |
||||
|
||||
#include "imx6ul-pinfunc.h" |
||||
/*
|
||||
* The pin function ID is a tuple of |
||||
* <mux_reg conf_reg input_reg mux_mode input_val> |
||||
*/ |
||||
#define MX6UL_PAD_ENET2_RX_DATA0__EPDC_SDDO08 0x00E4 0x0370 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_ENET2_RX_DATA1__EPDC_SDDO09 0x00E8 0x0374 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_ENET2_RX_EN__EPDC_SDDO10 0x00EC 0x0378 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA0__EPDC_SDDO11 0x00F0 0x037C 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_ENET2_TX_DATA1__EPDC_SDDO12 0x00F4 0x0380 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_ENET2_TX_EN__EPDC_SDDO13 0x00F8 0x0384 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_ENET2_TX_CLK__EPDC_SDDO14 0x00FC 0x0388 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_ENET2_RX_ER__EPDC_SDDO15 0x0100 0x038C 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_CLK__EPDC_SDCLK 0x0104 0x0390 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_ENABLE__EPDC_SDLE 0x0108 0x0394 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_HSYNC__EPDC_SDOE 0x010C 0x0398 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_VSYNC__EPDC_SDCE0 0x0110 0x039C 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_RESET__EPDC_GDOE 0x0114 0x03A0 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA00__EPDC_SDDO00 0x0118 0x03A4 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA01__EPDC_SDDO01 0x011C 0x03A8 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA02__EPDC_SDDO02 0x0120 0x03AC 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA03__EPDC_SDDO03 0x0124 0x03B0 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA04__EPDC_SDDO04 0x0128 0x03B4 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA05__EPDC_SDDO05 0x012C 0x03B8 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA06__EPDC_SDDO06 0x0130 0x03BC 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA07__EPDC_SDDO07 0x0134 0x03C0 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA14__EPDC_SDSHR 0x0150 0x03DC 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA15__EPDC_GDRL 0x0154 0x03E0 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA16__EPDC_GDCLK 0x0158 0x03E4 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA17__EPDC_GDSP 0x015C 0x03E8 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_LCD_DATA21__EPDC_SDCE1 0x016C 0x03F8 0x0000 0x9 0x0 |
||||
|
||||
#define MX6UL_PAD_CSI_MCLK__ESAI_TX3_RX2 0x01D4 0x0460 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_PIXCLK__ESAI_TX2_RX3 0x01D8 0x0464 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_VSYNC__ESAI_TX4_RX1 0x01DC 0x0468 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_HSYNC__ESAI_TX1 0x01E0 0x046C 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA00__ESAI_TX_HF_CLK 0x01E4 0x0470 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA01__ESAI_RX_HF_CLK 0x01E8 0x0474 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA02__ESAI_RX_FS 0x01EC 0x0478 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA03__ESAI_RX_CLK 0x01F0 0x047C 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA04__ESAI_TX_FS 0x01F4 0x0480 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA05__ESAI_TX_CLK 0x01F8 0x0484 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA06__ESAI_TX5_RX0 0x01FC 0x0488 0x0000 0x9 0x0 |
||||
#define MX6UL_PAD_CSI_DATA07__ESAI_T0 0x0200 0x048C 0x0000 0x9 0x0 |
||||
|
||||
#endif /* __DTS_IMX6ULL_PINFUNC_H */ |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,97 @@ |
||||
/* |
||||
* Copyright 2016 Toradex AG |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ or X11 |
||||
*/ |
||||
|
||||
/dts-v1/; |
||||
#include <dt-bindings/gpio/gpio.h> |
||||
#include "imx7.dtsi" |
||||
|
||||
/ { |
||||
model = "Toradex Colibri iMX7S/D"; |
||||
compatible = "toradex,imx7-colibri", "fsl,imx7"; |
||||
|
||||
chosen { |
||||
stdout-path = &uart1; |
||||
}; |
||||
}; |
||||
|
||||
&i2c1 { |
||||
pinctrl-names = "default", "gpio"; |
||||
pinctrl-0 = <&pinctrl_i2c1>; |
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>; |
||||
sda-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; |
||||
scl-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; |
||||
status = "okay"; |
||||
|
||||
rn5t567@33 { |
||||
compatible = "ricoh,rn5t567"; |
||||
reg = <0x33>; |
||||
}; |
||||
}; |
||||
|
||||
&i2c4 { |
||||
pinctrl-names = "default", "gpio"; |
||||
pinctrl-0 = <&pinctrl_i2c4>; |
||||
pinctrl-1 = <&pinctrl_i2c4_gpio>; |
||||
sda-gpios = <&gpio7 9 GPIO_ACTIVE_LOW>; |
||||
scl-gpios = <&gpio7 8 GPIO_ACTIVE_LOW>; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&uart1 { |
||||
pinctrl-names = "default"; |
||||
pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; |
||||
uart-has-rtscts; |
||||
fsl,dte-mode; |
||||
status = "okay"; |
||||
}; |
||||
|
||||
&iomuxc { |
||||
pinctrl_i2c4: i2c4-grp { |
||||
fsl,pins = < |
||||
MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f |
||||
MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_i2c4_gpio: i2c4-gpio-grp { |
||||
fsl,pins = < |
||||
MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f |
||||
MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_uart1: uart1-grp { |
||||
fsl,pins = < |
||||
MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX 0x79 |
||||
MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX 0x79 |
||||
MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS 0x79 |
||||
MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS 0x79 |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_uart1_ctrl1: uart1-ctrl1-grp { |
||||
fsl,pins = < |
||||
MX7D_PAD_SD2_DATA1__GPIO5_IO15 0x14 /* DCD */ |
||||
MX7D_PAD_SD2_DATA0__GPIO5_IO14 0x14 /* DTR */ |
||||
>; |
||||
}; |
||||
}; |
||||
|
||||
&iomuxc_lpsr { |
||||
pinctrl_i2c1: i2c1-grp { |
||||
fsl,pins = < |
||||
MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f |
||||
MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f |
||||
>; |
||||
}; |
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio-grp { |
||||
fsl,pins = < |
||||
MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f |
||||
MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f |
||||
>; |
||||
}; |
||||
}; |
@ -0,0 +1,194 @@ |
||||
/* |
||||
* Copyright 2016 Toradex AG |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ or X11 |
||||
*/ |
||||
#include "imx7d-pinfunc.h" |
||||
#include "skeleton.dtsi" |
||||
|
||||
/ { |
||||
aliases { |
||||
gpio0 = &gpio1; |
||||
gpio1 = &gpio2; |
||||
gpio2 = &gpio3; |
||||
gpio3 = &gpio4; |
||||
gpio4 = &gpio5; |
||||
gpio5 = &gpio6; |
||||
gpio6 = &gpio7; |
||||
i2c0 = &i2c1; |
||||
i2c1 = &i2c2; |
||||
i2c2 = &i2c3; |
||||
i2c3 = &i2c4; |
||||
serial0 = &uart1; |
||||
serial1 = &uart2; |
||||
serial2 = &uart3; |
||||
serial3 = &uart4; |
||||
serial4 = &uart5; |
||||
serial5 = &uart6; |
||||
serial6 = &uart7; |
||||
}; |
||||
|
||||
soc { |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
compatible = "simple-bus"; |
||||
ranges; |
||||
|
||||
aips1: aips-bus@30000000 { |
||||
compatible = "fsl,aips-bus", "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0x30000000 0x400000>; |
||||
ranges; |
||||
|
||||
gpio1: gpio@30200000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30200000 0x10000>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
}; |
||||
|
||||
gpio2: gpio@30210000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30210000 0x10000>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
}; |
||||
|
||||
gpio3: gpio@30220000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30220000 0x10000>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
}; |
||||
|
||||
gpio4: gpio@30230000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30230000 0x10000>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
}; |
||||
|
||||
gpio5: gpio@30240000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30240000 0x10000>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
}; |
||||
|
||||
gpio6: gpio@30250000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30250000 0x10000>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
}; |
||||
|
||||
gpio7: gpio@30260000 { |
||||
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; |
||||
reg = <0x30260000 0x10000>; |
||||
gpio-controller; |
||||
#gpio-cells = <2>; |
||||
}; |
||||
|
||||
iomuxc_lpsr: iomuxc-lpsr@302c0000 { |
||||
compatible = "fsl,imx7d-iomuxc-lpsr"; |
||||
reg = <0x302c0000 0x10000>; |
||||
fsl,input-sel = <&iomuxc>; |
||||
}; |
||||
|
||||
iomuxc: iomuxc@30330000 { |
||||
compatible = "fsl,imx7d-iomuxc"; |
||||
reg = <0x30330000 0x10000>; |
||||
}; |
||||
}; |
||||
|
||||
aips3: aips-bus@30800000 { |
||||
compatible = "fsl,aips-bus", "simple-bus"; |
||||
#address-cells = <1>; |
||||
#size-cells = <1>; |
||||
reg = <0x30800000 0x400000>; |
||||
ranges; |
||||
|
||||
uart1: serial@30860000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30860000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart2: serial@30890000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30890000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart3: serial@30880000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30880000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c1: i2c@30a20000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a20000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c2: i2c@30a30000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a30000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c3: i2c@30a40000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a40000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
i2c4: i2c@30a50000 { |
||||
#address-cells = <1>; |
||||
#size-cells = <0>; |
||||
compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; |
||||
reg = <0x30a50000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart4: serial@30a60000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a60000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart5: serial@30a70000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a70000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart6: serial@30a80000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a80000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
|
||||
uart7: serial@30a90000 { |
||||
compatible = "fsl,imx7d-uart", |
||||
"fsl,imx6q-uart"; |
||||
reg = <0x30a90000 0x10000>; |
||||
status = "disabled"; |
||||
}; |
||||
}; |
||||
}; |
||||
}; |
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,12 @@ |
||||
if TARGET_MX6ULL_14X14_EVK |
||||
|
||||
config SYS_BOARD |
||||
default "mx6ullevk" |
||||
|
||||
config SYS_VENDOR |
||||
default "freescale" |
||||
|
||||
config SYS_CONFIG_NAME |
||||
default "mx6ullevk" |
||||
|
||||
endif |
@ -0,0 +1,6 @@ |
||||
MX6ULLEVK BOARD |
||||
M: Peng Fan <peng.fan@nxp.com> |
||||
S: Maintained |
||||
F: board/freescale/mx6ullevk/ |
||||
F: include/configs/mx6ullevk.h |
||||
F: configs/mx6ull_14x14_evk_defconfig |
@ -0,0 +1,6 @@ |
||||
# (C) Copyright 2016 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# SPDX-License-Identifier: GPL-2.0+
|
||||
#
|
||||
|
||||
obj-y := mx6ullevk.o
|
@ -0,0 +1,116 @@ |
||||
/* |
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
* |
||||
* Refer docs/README.imxmage for more details about how-to configure |
||||
* and create imximage boot image |
||||
* |
||||
* The syntax is taken as close as possible with the kwbimage |
||||
*/ |
||||
|
||||
#define __ASSEMBLY__ |
||||
#include <config.h> |
||||
|
||||
/* image version */ |
||||
|
||||
IMAGE_VERSION 2 |
||||
|
||||
/* |
||||
* Boot Device : one of |
||||
* spi/sd/nand/onenand, qspi/nor |
||||
*/ |
||||
|
||||
#ifdef CONFIG_SYS_BOOT_QSPI |
||||
BOOT_FROM qspi |
||||
#elif defined(CONFIG_SYS_BOOT_EIMNOR) |
||||
BOOT_FROM nor |
||||
#else |
||||
BOOT_FROM sd |
||||
#endif |
||||
|
||||
#ifdef CONFIG_USE_PLUGIN |
||||
/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/ |
||||
PLUGIN board/freescale/mx6ullevk/plugin.bin 0x00907000 |
||||
#else |
||||
|
||||
#ifdef CONFIG_SECURE_BOOT |
||||
CSF CONFIG_CSF_SIZE |
||||
#endif |
||||
|
||||
/* |
||||
* Device Configuration Data (DCD) |
||||
* |
||||
* Each entry must have the format: |
||||
* Addr-type Address Value |
||||
* |
||||
* where: |
||||
* Addr-type register length (1,2 or 4 bytes) |
||||
* Address absolute address of the register |
||||
* value value to be stored in the register |
||||
*/ |
||||
|
||||
/* Enable all clocks */ |
||||
DATA 4 0x020c4068 0xffffffff |
||||
DATA 4 0x020c406c 0xffffffff |
||||
DATA 4 0x020c4070 0xffffffff |
||||
DATA 4 0x020c4074 0xffffffff |
||||
DATA 4 0x020c4078 0xffffffff |
||||
DATA 4 0x020c407c 0xffffffff |
||||
DATA 4 0x020c4080 0xffffffff |
||||
|
||||
DATA 4 0x020E04B4 0x000C0000 |
||||
DATA 4 0x020E04AC 0x00000000 |
||||
DATA 4 0x020E027C 0x00000030 |
||||
DATA 4 0x020E0250 0x00000030 |
||||
DATA 4 0x020E024C 0x00000030 |
||||
DATA 4 0x020E0490 0x00000030 |
||||
DATA 4 0x020E0288 0x000C0030 |
||||
DATA 4 0x020E0270 0x00000000 |
||||
DATA 4 0x020E0260 0x00000030 |
||||
DATA 4 0x020E0264 0x00000030 |
||||
DATA 4 0x020E04A0 0x00000030 |
||||
DATA 4 0x020E0494 0x00020000 |
||||
DATA 4 0x020E0280 0x00000030 |
||||
DATA 4 0x020E0284 0x00000030 |
||||
DATA 4 0x020E04B0 0x00020000 |
||||
DATA 4 0x020E0498 0x00000030 |
||||
DATA 4 0x020E04A4 0x00000030 |
||||
DATA 4 0x020E0244 0x00000030 |
||||
DATA 4 0x020E0248 0x00000030 |
||||
DATA 4 0x021B001C 0x00008000 |
||||
DATA 4 0x021B0800 0xA1390003 |
||||
DATA 4 0x021B080C 0x00000004 |
||||
DATA 4 0x021B083C 0x41640158 |
||||
DATA 4 0x021B0848 0x40403237 |
||||
DATA 4 0x021B0850 0x40403C33 |
||||
DATA 4 0x021B081C 0x33333333 |
||||
DATA 4 0x021B0820 0x33333333 |
||||
DATA 4 0x021B082C 0xf3333333 |
||||
DATA 4 0x021B0830 0xf3333333 |
||||
DATA 4 0x021B08C0 0x00944009 |
||||
DATA 4 0x021B08b8 0x00000800 |
||||
DATA 4 0x021B0004 0x0002002D |
||||
DATA 4 0x021B0008 0x1B333030 |
||||
DATA 4 0x021B000C 0x676B52F3 |
||||
DATA 4 0x021B0010 0xB66D0B63 |
||||
DATA 4 0x021B0014 0x01FF00DB |
||||
DATA 4 0x021B0018 0x00201740 |
||||
DATA 4 0x021B001C 0x00008000 |
||||
DATA 4 0x021B002C 0x000026D2 |
||||
DATA 4 0x021B0030 0x006B1023 |
||||
DATA 4 0x021B0040 0x0000004F |
||||
DATA 4 0x021B0000 0x84180000 |
||||
DATA 4 0x021B0890 0x00400000 |
||||
DATA 4 0x021B001C 0x02008032 |
||||
DATA 4 0x021B001C 0x00008033 |
||||
DATA 4 0x021B001C 0x00048031 |
||||
DATA 4 0x021B001C 0x15208030 |
||||
DATA 4 0x021B001C 0x04008040 |
||||
DATA 4 0x021B0020 0x00000800 |
||||
DATA 4 0x021B0818 0x00000227 |
||||
DATA 4 0x021B0004 0x0002552D |
||||
DATA 4 0x021B0404 0x00011006 |
||||
DATA 4 0x021B001C 0x00000000 |
||||
|
||||
#endif |
@ -0,0 +1,99 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <asm/arch/clock.h> |
||||
#include <asm/arch/iomux.h> |
||||
#include <asm/arch/imx-regs.h> |
||||
#include <asm/arch/crm_regs.h> |
||||
#include <asm/arch/mx6-pins.h> |
||||
#include <asm/arch/sys_proto.h> |
||||
#include <asm/gpio.h> |
||||
#include <asm/imx-common/iomux-v3.h> |
||||
#include <asm/imx-common/boot_mode.h> |
||||
#include <asm/io.h> |
||||
#include <common.h> |
||||
#include <fsl_esdhc.h> |
||||
#include <linux/sizes.h> |
||||
#include <mmc.h> |
||||
|
||||
DECLARE_GLOBAL_DATA_PTR; |
||||
|
||||
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ |
||||
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
|
||||
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) |
||||
|
||||
int dram_init(void) |
||||
{ |
||||
gd->ram_size = imx_ddr_size(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static iomux_v3_cfg_t const uart1_pads[] = { |
||||
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
||||
}; |
||||
|
||||
static void setup_iomux_uart(void) |
||||
{ |
||||
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
||||
} |
||||
|
||||
int board_mmc_get_env_dev(int devno) |
||||
{ |
||||
return devno; |
||||
} |
||||
|
||||
int mmc_map_to_kernel_blk(int devno) |
||||
{ |
||||
return devno; |
||||
} |
||||
|
||||
int board_early_init_f(void) |
||||
{ |
||||
setup_iomux_uart(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int board_init(void) |
||||
{ |
||||
/* Address of boot parameters */ |
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
#ifdef CONFIG_CMD_BMODE |
||||
static const struct boot_mode board_boot_modes[] = { |
||||
/* 4 bit bus width */ |
||||
{"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)}, |
||||
{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)}, |
||||
{"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)}, |
||||
{NULL, 0}, |
||||
}; |
||||
#endif |
||||
|
||||
int board_late_init(void) |
||||
{ |
||||
#ifdef CONFIG_CMD_BMODE |
||||
add_board_boot_modes(board_boot_modes); |
||||
#endif |
||||
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
||||
setenv("board_name", "EVK"); |
||||
setenv("board_rev", "14X14"); |
||||
#endif |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int checkboard(void) |
||||
{ |
||||
puts("Board: MX6ULL 14x14 EVK\n"); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,21 @@ |
||||
How to use U-Boot on MX6Q/DL Udoo boards |
||||
---------------------------------------- |
||||
|
||||
- Build U-Boot for MX6Q/DL Udoo boards: |
||||
|
||||
$ make mrproper |
||||
$ make udoo_defconfig |
||||
$ make |
||||
|
||||
This will generate the SPL image called SPL and the u-boot.img. |
||||
|
||||
- Flash the SPL image into the SD card: |
||||
|
||||
sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync |
||||
|
||||
- Flash the u-boot.img image into the SD card: |
||||
|
||||
sudo dd if=u-boot.img of=/dev/mmcblk0 bs=1k seek=69; sync |
||||
|
||||
- Insert the SD card in the board, power it up and U-Boot messages should |
||||
come up. |
@ -0,0 +1,33 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_TARGET_BK4R1=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="bk4r1" |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/phytec/pcm052/imximage.cfg,ENV_IS_IN_NAND" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_SF=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_MII=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_VYBRID_GPIO=y |
||||
CONFIG_NAND_VF610_NFC=y |
||||
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y |
||||
CONFIG_DM_SERIAL=y |
||||
CONFIG_FSL_LPUART=y |
||||
CONFIG_DM_SPI=y |
||||
CONFIG_FSL_QSPI=y |
||||
CONFIG_DM_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH=y |
||||
CONFIG_SPI_FLASH_STMICRO=y |
||||
CONFIG_SPI_FLASH_MTD=y |
||||
CONFIG_CMD_DM=y |
||||
CONFIG_CMD_UBI=y |
@ -0,0 +1,30 @@ |
||||
CONFIG_ARM=y |
||||
CONFIG_ARCH_MX6=y |
||||
CONFIG_TARGET_MX6ULL_14X14_EVK=y |
||||
CONFIG_DM_GPIO=y |
||||
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-14x14-evk" |
||||
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6ullevk/imximage.cfg" |
||||
CONFIG_BOOTDELAY=3 |
||||
CONFIG_HUSH_PARSER=y |
||||
CONFIG_CMD_BOOTZ=y |
||||
# CONFIG_CMD_IMLS is not set |
||||
CONFIG_CMD_MEMTEST=y |
||||
CONFIG_CMD_MMC=y |
||||
CONFIG_CMD_I2C=y |
||||
CONFIG_CMD_GPIO=y |
||||
CONFIG_CMD_DHCP=y |
||||
CONFIG_CMD_PING=y |
||||
CONFIG_CMD_CACHE=y |
||||
CONFIG_CMD_EXT2=y |
||||
CONFIG_CMD_EXT4=y |
||||
CONFIG_CMD_EXT4_WRITE=y |
||||
CONFIG_CMD_FAT=y |
||||
CONFIG_CMD_FS_GENERIC=y |
||||
CONFIG_OF_CONTROL=y |
||||
CONFIG_DM_74X164=y |
||||
CONFIG_DM_I2C=y |
||||
CONFIG_DM_MMC=y |
||||
CONFIG_PINCTRL=y |
||||
CONFIG_PINCTRL_IMX6=y |
||||
CONFIG_DM_REGULATOR=y |
||||
CONFIG_DM_SPI=y |
@ -0,0 +1,17 @@ |
||||
Ricoh RN5T567 PMIC |
||||
|
||||
This file describes the binding info for the PMIC driver. |
||||
|
||||
Required properties: |
||||
- compatible: "ricoh,rn5t567" |
||||
- reg: depending on strapping, e.g. 0x33 |
||||
|
||||
With those two properties, the PMIC device can be used to read/write |
||||
registers. |
||||
|
||||
Example: |
||||
|
||||
rn5t567@33 { |
||||
compatible = "ricoh,rn5t567"; |
||||
reg = <0x33>; |
||||
}; |
@ -0,0 +1,8 @@ |
||||
NXP i.MX (MXC) UART |
||||
|
||||
Required properties: |
||||
- compatible: must be "fsl,imx7d-uart" |
||||
- reg: start address and size of the registers |
||||
|
||||
Optional properties: |
||||
- fsl,dte-mode: use DTE mode |
@ -0,0 +1,64 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Toradex AG |
||||
* Stefan Agner <stefan.agner@toradex.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <dm.h> |
||||
#include <errno.h> |
||||
#include <fdtdec.h> |
||||
#include <libfdt.h> |
||||
#include <power/rn5t567_pmic.h> |
||||
#include <power/pmic.h> |
||||
|
||||
static int rn5t567_reg_count(struct udevice *dev) |
||||
{ |
||||
return RN5T567_NUM_OF_REGS; |
||||
} |
||||
|
||||
static int rn5t567_write(struct udevice *dev, uint reg, const uint8_t *buff, |
||||
int len) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = dm_i2c_write(dev, reg, buff, len); |
||||
if (ret) { |
||||
debug("write error to device: %p register: %#x!", dev, reg); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int rn5t567_read(struct udevice *dev, uint reg, uint8_t *buff, int len) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = dm_i2c_read(dev, reg, buff, len); |
||||
if (ret) { |
||||
debug("read error from device: %p register: %#x!", dev, reg); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct dm_pmic_ops rn5t567_ops = { |
||||
.reg_count = rn5t567_reg_count, |
||||
.read = rn5t567_read, |
||||
.write = rn5t567_write, |
||||
}; |
||||
|
||||
static const struct udevice_id rn5t567_ids[] = { |
||||
{ .compatible = "ricoh,rn5t567" }, |
||||
{ } |
||||
}; |
||||
|
||||
U_BOOT_DRIVER(pmic_rn5t567) = { |
||||
.name = "rn5t567 pmic", |
||||
.id = UCLASS_PMIC, |
||||
.of_match = rn5t567_ids, |
||||
.ops = &rn5t567_ops, |
||||
}; |
@ -0,0 +1,33 @@ |
||||
/*
|
||||
* Copyright 2016 3ADEV <http://3adev.com>
|
||||
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> |
||||
* |
||||
* Configuration settings for the phytec PCM-052 SoM-based BK4R1. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
/* Define the BK4r1-specific env commands */ |
||||
#define PCM052_EXTRA_ENV_SETTINGS \ |
||||
"set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \
|
||||
"set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0" |
||||
|
||||
/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ |
||||
#define PCM052_BOOTCOMMAND "run set_gpio103; sf probe; " |
||||
|
||||
/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ |
||||
#define PCM052_NET_INIT "run set_gpio122; " |
||||
|
||||
/* add NOR to MTD env */ |
||||
#define MTDIDS_DEFAULT "nand0=NAND,nor0=NOR" |
||||
#define MTDPARTS_DEFAULT "mtdparts=NAND:640k(bootloader)"\ |
||||
",128k(env1)"\
|
||||
",128k(env2)"\
|
||||
",128k(dtb)"\
|
||||
",6144k(kernel)"\
|
||||
",-(root);"\
|
||||
"NOR:-(nor)" |
||||
|
||||
/* now include standard PCM052 config */ |
||||
|
||||
#include "configs/pcm052.h" |
@ -0,0 +1,180 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* Configuration settings for the Freescale i.MX6UL 14x14 EVK board. |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __MX6ULLEVK_CONFIG_H |
||||
#define __MX6ULLEVK_CONFIG_H |
||||
|
||||
|
||||
#include <asm/arch/imx-regs.h> |
||||
#include <linux/sizes.h> |
||||
#include "mx6_common.h" |
||||
#include <asm/imx-common/gpio.h> |
||||
|
||||
#ifdef CONFIG_SECURE_BOOT |
||||
#ifndef CONFIG_CSF_SIZE |
||||
#define CONFIG_CSF_SIZE 0x4000 |
||||
#endif |
||||
#endif |
||||
|
||||
#define PHYS_SDRAM_SIZE SZ_512M |
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
||||
|
||||
#define CONFIG_DISPLAY_CPUINFO |
||||
#define CONFIG_DISPLAY_BOARDINFO |
||||
|
||||
/* Size of malloc() pool */ |
||||
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) |
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F |
||||
#define CONFIG_BOARD_LATE_INIT |
||||
|
||||
#define CONFIG_MXC_GPIO |
||||
|
||||
#define CONFIG_MXC_UART |
||||
#define CONFIG_MXC_UART_BASE UART1_BASE |
||||
|
||||
/* MMC Configs */ |
||||
#ifdef CONFIG_FSL_USDHC |
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR |
||||
|
||||
/* NAND pin conflicts with usdhc2 */ |
||||
#ifdef CONFIG_SYS_USE_NAND |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 1 |
||||
#else |
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2 |
||||
#endif |
||||
#endif |
||||
|
||||
/* I2C configs */ |
||||
#ifdef CONFIG_CMD_I2C |
||||
#define CONFIG_SYS_I2C_MXC |
||||
#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
||||
#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
||||
#define CONFIG_SYS_I2C_SPEED 100000 |
||||
#endif |
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 |
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \ |
||||
"script=boot.scr\0" \
|
||||
"image=zImage\0" \
|
||||
"console=ttymxc0\0" \
|
||||
"fdt_high=0xffffffff\0" \
|
||||
"initrd_high=0xffffffff\0" \
|
||||
"fdt_file=imx6ull-14x14-evk.dtb\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"ip_dyn=yes\0" \
|
||||
"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=${mmcroot}\0" \
|
||||
"loadbootscript=" \
|
||||
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console},${baudrate} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"bootz ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"if test ${boot_fdt} = try; then " \
|
||||
"bootz; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"bootz; " \
|
||||
"fi;\0" \
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \ |
||||
"mmc dev ${mmcdev};" \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else run netboot; fi" |
||||
|
||||
/* Miscellaneous configurable options */ |
||||
#define CONFIG_SYS_MEMTEST_START 0x80000000 |
||||
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) |
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
||||
#define CONFIG_SYS_HZ 1000 |
||||
|
||||
#define CONFIG_STACKSIZE SZ_128K |
||||
|
||||
/* Physical Memory Map */ |
||||
#define CONFIG_NR_DRAM_BANKS 1 |
||||
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR |
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM |
||||
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR |
||||
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE |
||||
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET \ |
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
||||
#define CONFIG_SYS_INIT_SP_ADDR \ |
||||
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) |
||||
|
||||
/* FLASH and environment organization */ |
||||
#define CONFIG_SYS_NO_FLASH |
||||
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ |
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ |
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ |
||||
|
||||
#define CONFIG_ENV_IS_IN_MMC |
||||
#define CONFIG_ENV_SIZE SZ_8K |
||||
#define CONFIG_ENV_OFFSET (12 * SZ_64K) |
||||
|
||||
#define CONFIG_CMD_BMODE |
||||
|
||||
#define CONFIG_IMX_THERMAL |
||||
|
||||
#define CONFIG_IOMUX_LPSR |
||||
|
||||
#define CONFIG_SOFT_SPI |
||||
|
||||
#endif |
@ -0,0 +1,253 @@ |
||||
/*
|
||||
* Copyright (C) 2015-2016 Freescale Semiconductor, Inc. |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
*/ |
||||
|
||||
#ifndef __DT_BINDINGS_CLOCK_IMX6UL_H |
||||
#define __DT_BINDINGS_CLOCK_IMX6UL_H |
||||
|
||||
#define IMX6UL_CLK_DUMMY 0 |
||||
#define IMX6UL_CLK_CKIL 1 |
||||
#define IMX6UL_CLK_CKIH 2 |
||||
#define IMX6UL_CLK_OSC 3 |
||||
#define IMX6UL_PLL1_BYPASS_SRC 4 |
||||
#define IMX6UL_PLL2_BYPASS_SRC 5 |
||||
#define IMX6UL_PLL3_BYPASS_SRC 6 |
||||
#define IMX6UL_PLL4_BYPASS_SRC 7 |
||||
#define IMX6UL_PLL5_BYPASS_SRC 8 |
||||
#define IMX6UL_PLL6_BYPASS_SRC 9 |
||||
#define IMX6UL_PLL7_BYPASS_SRC 10 |
||||
#define IMX6UL_CLK_PLL1 11 |
||||
#define IMX6UL_CLK_PLL2 12 |
||||
#define IMX6UL_CLK_PLL3 13 |
||||
#define IMX6UL_CLK_PLL4 14 |
||||
#define IMX6UL_CLK_PLL5 15 |
||||
#define IMX6UL_CLK_PLL6 16 |
||||
#define IMX6UL_CLK_PLL7 17 |
||||
#define IMX6UL_PLL1_BYPASS 18 |
||||
#define IMX6UL_PLL2_BYPASS 19 |
||||
#define IMX6UL_PLL3_BYPASS 20 |
||||
#define IMX6UL_PLL4_BYPASS 21 |
||||
#define IMX6UL_PLL5_BYPASS 22 |
||||
#define IMX6UL_PLL6_BYPASS 23 |
||||
#define IMX6UL_PLL7_BYPASS 24 |
||||
#define IMX6UL_CLK_PLL1_SYS 25 |
||||
#define IMX6UL_CLK_PLL2_BUS 26 |
||||
#define IMX6UL_CLK_PLL3_USB_OTG 27 |
||||
#define IMX6UL_CLK_PLL4_AUDIO 28 |
||||
#define IMX6UL_CLK_PLL5_VIDEO 29 |
||||
#define IMX6UL_CLK_PLL6_ENET 30 |
||||
#define IMX6UL_CLK_PLL7_USB_HOST 31 |
||||
#define IMX6UL_CLK_USBPHY1 32 |
||||
#define IMX6UL_CLK_USBPHY2 33 |
||||
#define IMX6UL_CLK_USBPHY1_GATE 34 |
||||
#define IMX6UL_CLK_USBPHY2_GATE 35 |
||||
#define IMX6UL_CLK_PLL2_PFD0 36 |
||||
#define IMX6UL_CLK_PLL2_PFD1 37 |
||||
#define IMX6UL_CLK_PLL2_PFD2 38 |
||||
#define IMX6UL_CLK_PLL2_PFD3 39 |
||||
#define IMX6UL_CLK_PLL3_PFD0 40 |
||||
#define IMX6UL_CLK_PLL3_PFD1 41 |
||||
#define IMX6UL_CLK_PLL3_PFD2 42 |
||||
#define IMX6UL_CLK_PLL3_PFD3 43 |
||||
#define IMX6UL_CLK_ENET_REF 44 |
||||
#define IMX6UL_CLK_ENET2_REF 45 |
||||
#define IMX6UL_CLK_ENET2_REF_125M 46 |
||||
#define IMX6UL_CLK_ENET_PTP_REF 47 |
||||
#define IMX6UL_CLK_ENET_PTP 48 |
||||
#define IMX6UL_CLK_PLL4_POST_DIV 49 |
||||
#define IMX6UL_CLK_PLL4_AUDIO_DIV 50 |
||||
#define IMX6UL_CLK_PLL5_POST_DIV 51 |
||||
#define IMX6UL_CLK_PLL5_VIDEO_DIV 52 |
||||
#define IMX6UL_CLK_PLL2_198M 53 |
||||
#define IMX6UL_CLK_PLL3_80M 54 |
||||
#define IMX6UL_CLK_PLL3_60M 55 |
||||
#define IMX6UL_CLK_STEP 56 |
||||
#define IMX6UL_CLK_PLL1_SW 57 |
||||
#define IMX6UL_CLK_AXI_ALT_SEL 58 |
||||
#define IMX6UL_CLK_AXI_SEL 59 |
||||
#define IMX6UL_CLK_PERIPH_PRE 60 |
||||
#define IMX6UL_CLK_PERIPH2_PRE 61 |
||||
#define IMX6UL_CLK_PERIPH_CLK2_SEL 62 |
||||
#define IMX6UL_CLK_PERIPH2_CLK2_SEL 63 |
||||
#define IMX6UL_CLK_USDHC1_SEL 64 |
||||
#define IMX6UL_CLK_USDHC2_SEL 65 |
||||
#define IMX6UL_CLK_BCH_SEL 66 |
||||
#define IMX6UL_CLK_GPMI_SEL 67 |
||||
#define IMX6UL_CLK_EIM_SLOW_SEL 68 |
||||
#define IMX6UL_CLK_SPDIF_SEL 69 |
||||
#define IMX6UL_CLK_SAI1_SEL 70 |
||||
#define IMX6UL_CLK_SAI2_SEL 71 |
||||
#define IMX6UL_CLK_SAI3_SEL 72 |
||||
#define IMX6UL_CLK_LCDIF_PRE_SEL 73 |
||||
#define IMX6UL_CLK_SIM_PRE_SEL 74 |
||||
#define IMX6UL_CLK_LDB_DI0_SEL 75 |
||||
#define IMX6UL_CLK_LDB_DI1_SEL 76 |
||||
#define IMX6UL_CLK_ENFC_SEL 77 |
||||
#define IMX6UL_CLK_CAN_SEL 78 |
||||
#define IMX6UL_CLK_ECSPI_SEL 79 |
||||
#define IMX6UL_CLK_UART_SEL 80 |
||||
#define IMX6UL_CLK_QSPI1_SEL 81 |
||||
#define IMX6UL_CLK_PERCLK_SEL 82 |
||||
#define IMX6UL_CLK_LCDIF_SEL 83 |
||||
#define IMX6UL_CLK_SIM_SEL 84 |
||||
#define IMX6UL_CLK_PERIPH 85 |
||||
#define IMX6UL_CLK_PERIPH2 86 |
||||
#define IMX6UL_CLK_LDB_DI0_DIV_3_5 87 |
||||
#define IMX6UL_CLK_LDB_DI0_DIV_7 88 |
||||
#define IMX6UL_CLK_LDB_DI1_DIV_3_5 89 |
||||
#define IMX6UL_CLK_LDB_DI1_DIV_7 90 |
||||
#define IMX6UL_CLK_LDB_DI0_DIV_SEL 91 |
||||
#define IMX6UL_CLK_LDB_DI1_DIV_SEL 92 |
||||
#define IMX6UL_CLK_ARM 93 |
||||
#define IMX6UL_CLK_PERIPH_CLK2 94 |
||||
#define IMX6UL_CLK_PERIPH2_CLK2 95 |
||||
#define IMX6UL_CLK_AHB 96 |
||||
#define IMX6UL_CLK_MMDC_PODF 97 |
||||
#define IMX6UL_CLK_AXI_PODF 98 |
||||
#define IMX6UL_CLK_PERCLK 99 |
||||
#define IMX6UL_CLK_IPG 100 |
||||
#define IMX6UL_CLK_USDHC1_PODF 101 |
||||
#define IMX6UL_CLK_USDHC2_PODF 102 |
||||
#define IMX6UL_CLK_BCH_PODF 103 |
||||
#define IMX6UL_CLK_GPMI_PODF 104 |
||||
#define IMX6UL_CLK_EIM_SLOW_PODF 105 |
||||
#define IMX6UL_CLK_SPDIF_PRED 106 |
||||
#define IMX6UL_CLK_SPDIF_PODF 107 |
||||
#define IMX6UL_CLK_SAI1_PRED 108 |
||||
#define IMX6UL_CLK_SAI1_PODF 109 |
||||
#define IMX6UL_CLK_SAI2_PRED 110 |
||||
#define IMX6UL_CLK_SAI2_PODF 111 |
||||
#define IMX6UL_CLK_SAI3_PRED 112 |
||||
#define IMX6UL_CLK_SAI3_PODF 113 |
||||
#define IMX6UL_CLK_LCDIF_PRED 114 |
||||
#define IMX6UL_CLK_LCDIF_PODF 115 |
||||
#define IMX6UL_CLK_SIM_PODF 116 |
||||
#define IMX6UL_CLK_QSPI1_PDOF 117 |
||||
#define IMX6UL_CLK_ENFC_PRED 118 |
||||
#define IMX6UL_CLK_ENFC_PODF 119 |
||||
#define IMX6UL_CLK_CAN_PODF 120 |
||||
#define IMX6UL_CLK_ECSPI_PODF 121 |
||||
#define IMX6UL_CLK_UART_PODF 122 |
||||
#define IMX6UL_CLK_ADC1 123 |
||||
#define IMX6UL_CLK_ADC2 124 |
||||
#define IMX6UL_CLK_AIPSTZ1 125 |
||||
#define IMX6UL_CLK_AIPSTZ2 126 |
||||
#define IMX6UL_CLK_AIPSTZ3 127 |
||||
#define IMX6UL_CLK_APBHDMA 128 |
||||
#define IMX6UL_CLK_ASRC_IPG 129 |
||||
#define IMX6UL_CLK_ASRC_MEM 130 |
||||
#define IMX6UL_CLK_GPMI_BCH_APB 131 |
||||
#define IMX6UL_CLK_GPMI_BCH 132 |
||||
#define IMX6UL_CLK_GPMI_IO 133 |
||||
#define IMX6UL_CLK_GPMI_APB 134 |
||||
#define IMX6UL_CLK_CAAM_MEM 135 |
||||
#define IMX6UL_CLK_CAAM_ACLK 136 |
||||
#define IMX6UL_CLK_CAAM_IPG 137 |
||||
#define IMX6UL_CLK_CSI 138 |
||||
#define IMX6UL_CLK_ECSPI1 139 |
||||
#define IMX6UL_CLK_ECSPI2 140 |
||||
#define IMX6UL_CLK_ECSPI3 141 |
||||
#define IMX6UL_CLK_ECSPI4 142 |
||||
#define IMX6UL_CLK_EIM 143 |
||||
#define IMX6UL_CLK_ENET 144 |
||||
#define IMX6UL_CLK_ENET_AHB 145 |
||||
#define IMX6UL_CLK_EPIT1 146 |
||||
#define IMX6UL_CLK_EPIT2 147 |
||||
#define IMX6UL_CLK_CAN1_IPG 148 |
||||
#define IMX6UL_CLK_CAN1_SERIAL 149 |
||||
#define IMX6UL_CLK_CAN2_IPG 150 |
||||
#define IMX6UL_CLK_CAN2_SERIAL 151 |
||||
#define IMX6UL_CLK_GPT1_BUS 152 |
||||
#define IMX6UL_CLK_GPT1_SERIAL 153 |
||||
#define IMX6UL_CLK_GPT2_BUS 154 |
||||
#define IMX6UL_CLK_GPT2_SERIAL 155 |
||||
#define IMX6UL_CLK_I2C1 156 |
||||
#define IMX6UL_CLK_I2C2 157 |
||||
#define IMX6UL_CLK_I2C3 158 |
||||
#define IMX6UL_CLK_I2C4 159 |
||||
#define IMX6UL_CLK_IOMUXC 160 |
||||
#define IMX6UL_CLK_LCDIF_APB 161 |
||||
#define IMX6UL_CLK_LCDIF_PIX 162 |
||||
#define IMX6UL_CLK_MMDC_P0_FAST 163 |
||||
#define IMX6UL_CLK_MMDC_P0_IPG 164 |
||||
#define IMX6UL_CLK_OCOTP 165 |
||||
#define IMX6UL_CLK_OCRAM 166 |
||||
#define IMX6UL_CLK_PWM1 167 |
||||
#define IMX6UL_CLK_PWM2 168 |
||||
#define IMX6UL_CLK_PWM3 169 |
||||
#define IMX6UL_CLK_PWM4 170 |
||||
#define IMX6UL_CLK_PWM5 171 |
||||
#define IMX6UL_CLK_PWM6 172 |
||||
#define IMX6UL_CLK_PWM7 173 |
||||
#define IMX6UL_CLK_PWM8 174 |
||||
#define IMX6UL_CLK_PXP 175 |
||||
#define IMX6UL_CLK_QSPI 176 |
||||
#define IMX6UL_CLK_ROM 177 |
||||
#define IMX6UL_CLK_SAI1 178 |
||||
#define IMX6UL_CLK_SAI1_IPG 179 |
||||
#define IMX6UL_CLK_SAI2 180 |
||||
#define IMX6UL_CLK_SAI2_IPG 181 |
||||
#define IMX6UL_CLK_SAI3 182 |
||||
#define IMX6UL_CLK_SAI3_IPG 183 |
||||
#define IMX6UL_CLK_SDMA 184 |
||||
#define IMX6UL_CLK_SIM 185 |
||||
#define IMX6UL_CLK_SIM_S 186 |
||||
#define IMX6UL_CLK_SPBA 187 |
||||
#define IMX6UL_CLK_SPDIF 188 |
||||
#define IMX6UL_CLK_UART1_IPG 189 |
||||
#define IMX6UL_CLK_UART1_SERIAL 190 |
||||
#define IMX6UL_CLK_UART2_IPG 191 |
||||
#define IMX6UL_CLK_UART2_SERIAL 192 |
||||
#define IMX6UL_CLK_UART3_IPG 193 |
||||
#define IMX6UL_CLK_UART3_SERIAL 194 |
||||
#define IMX6UL_CLK_UART4_IPG 195 |
||||
#define IMX6UL_CLK_UART4_SERIAL 196 |
||||
#define IMX6UL_CLK_UART5_IPG 197 |
||||
#define IMX6UL_CLK_UART5_SERIAL 198 |
||||
#define IMX6UL_CLK_UART6_IPG 199 |
||||
#define IMX6UL_CLK_UART6_SERIAL 200 |
||||
#define IMX6UL_CLK_UART7_IPG 201 |
||||
#define IMX6UL_CLK_UART7_SERIAL 202 |
||||
#define IMX6UL_CLK_UART8_IPG 203 |
||||
#define IMX6UL_CLK_UART8_SERIAL 204 |
||||
#define IMX6UL_CLK_USBOH3 205 |
||||
#define IMX6UL_CLK_USDHC1 206 |
||||
#define IMX6UL_CLK_USDHC2 207 |
||||
#define IMX6UL_CLK_WDOG1 208 |
||||
#define IMX6UL_CLK_WDOG2 209 |
||||
#define IMX6UL_CLK_WDOG3 210 |
||||
#define IMX6UL_CLK_LDB_DI0 211 |
||||
#define IMX6UL_CLK_AXI 212 |
||||
#define IMX6UL_CLK_SPDIF_GCLK 213 |
||||
#define IMX6UL_CLK_GPT_3M 214 |
||||
#define IMX6UL_CLK_SIM2 215 |
||||
#define IMX6UL_CLK_SIM1 216 |
||||
#define IMX6UL_CLK_IPP_DI0 217 |
||||
#define IMX6UL_CLK_IPP_DI1 218 |
||||
#define IMX6UL_CA7_SECONDARY_SEL 219 |
||||
#define IMX6UL_CLK_PER_BCH 220 |
||||
#define IMX6UL_CLK_CSI_SEL 221 |
||||
#define IMX6UL_CLK_CSI_PODF 222 |
||||
#define IMX6UL_CLK_PLL3_120M 223 |
||||
/* For i.MX6ULL */ |
||||
#define IMX6UL_CLK_ESAI_SEL 224 |
||||
#define IMX6UL_CLK_ESAI_PRED 225 |
||||
#define IMX6UL_CLK_ESAI_PODF 226 |
||||
#define IMX6UL_CLK_ESAI_EXTAL 227 |
||||
#define IMX6UL_CLK_ESAI_MEM 228 |
||||
#define IMX6UL_CLK_ESAI_IPG 229 |
||||
#define IMX6UL_CLK_DCP_CLK 230 |
||||
#define IMX6UL_CLK_EPDC_PRE_SEL 231 |
||||
#define IMX6UL_CLK_EPDC_SEL 232 |
||||
#define IMX6UL_CLK_EPDC_PODF 233 |
||||
#define IMX6UL_CLK_EPDC_ACLK 234 |
||||
#define IMX6UL_CLK_EPDC_PIX 235 |
||||
|
||||
#define IMX6UL_CLK_END 236 |
||||
|
||||
#endif /* __DT_BINDINGS_CLOCK_IMX6UL_H */ |
@ -0,0 +1,113 @@ |
||||
/*
|
||||
* Copyright (C) 2016 Toradex AG |
||||
* Stefan Agner <stefan.agner@toradex.com> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
#ifndef __RN5T567_PMIC_H_ |
||||
#define __RN5T567_PMIC_H_ |
||||
|
||||
/* RN5T567 registers */ |
||||
enum { |
||||
RN5T567_LSIVER = 0x00, |
||||
RN5T567_OTPVER = 0x01, |
||||
RN5T567_IODAC = 0x02, |
||||
RN5T567_VINDAC = 0x03, |
||||
RN5T567_OUT32KEN = 0x05, |
||||
|
||||
RN5T567_CPUCNT = 0x06, |
||||
|
||||
RN5T567_PSWR = 0x07, |
||||
RN5T567_PONHIS = 0x09, |
||||
RN5T567_POFFHIS = 0x0A, |
||||
RN5T567_WATCHDOG = 0x0B, |
||||
RN5T567_WATCHDOGCNT = 0x0C, |
||||
RN5T567_PWRFUNC = 0x0D, |
||||
RN5T567_SLPCNT = 0x0E, |
||||
RN5T567_REPCNT = 0x0F, |
||||
RN5T567_PWRONTIMSET = 0x10, |
||||
RN5T567_NOETIMSETCNT = 0x11, |
||||
RN5T567_PWRIREN = 0x12, |
||||
RN5T567_PWRIRQ = 0x13, |
||||
RN5T567_PWRMON = 0x14, |
||||
RN5T567_PWRIRSEL = 0x15, |
||||
|
||||
RN5T567_DC1_SLOT = 0x16, |
||||
RN5T567_DC2_SLOT = 0x17, |
||||
RN5T567_DC3_SLOT = 0x18, |
||||
RN5T567_DC4_SLOT = 0x19, |
||||
|
||||
RN5T567_LDO1_SLOT = 0x1B, |
||||
RN5T567_LDO2_SLOT = 0x1C, |
||||
RN5T567_LDO3_SLOT = 0x1D, |
||||
RN5T567_LDO4_SLOT = 0x1E, |
||||
RN5T567_LDO5_SLOT = 0x1F, |
||||
|
||||
RN5T567_PSO0_SLOT = 0x25, |
||||
RN5T567_PSO1_SLOT = 0x26, |
||||
RN5T567_PSO2_SLOT = 0x27, |
||||
RN5T567_PSO3_SLOT = 0x28, |
||||
|
||||
RN5T567_LDORTC1_SLOT = 0x2A, |
||||
|
||||
RN5T567_DC1CTL = 0x2C, |
||||
RN5T567_DC1CTL2 = 0x2D, |
||||
RN5T567_DC2CTL = 0x2E, |
||||
RN5T567_DC2CTL2 = 0x2F, |
||||
RN5T567_DC3CTL = 0x30, |
||||
RN5T567_DC3CTL2 = 0x31, |
||||
RN5T567_DC4CTL = 0x32, |
||||
RN5T567_DC4CTL2 = 0x33, |
||||
|
||||
RN5T567_DC1DAC = 0x36, |
||||
RN5T567_DC2DAC = 0x37, |
||||
RN5T567_DC3DAC = 0x38, |
||||
RN5T567_DC4DAC = 0x39, |
||||
|
||||
RN5T567_DC1DAC_SLP = 0x3B, |
||||
RN5T567_DC2DAC_SLP = 0x3C, |
||||
RN5T567_DC3DAC_SLP = 0x3D, |
||||
RN5T567_DC4DAC_SLP = 0x3E, |
||||
|
||||
RN5T567_DCIREN = 0x40, |
||||
RN5T567_DCIRQ = 0x41, |
||||
RN5T567_DCIRMON = 0x42, |
||||
|
||||
RN5T567_LDOEN1 = 0x44, |
||||
RN5T567_LDOEN2 = 0x45, |
||||
RN5T567_LDODIS1 = 0x46, |
||||
|
||||
RN5T567_LDO1DAC = 0x4C, |
||||
RN5T567_LDO2DAC = 0x4D, |
||||
RN5T567_LDO3DAC = 0x4E, |
||||
RN5T567_LDO4DAC = 0x4F, |
||||
RN5T567_LDO5DAC = 0x50, |
||||
|
||||
RN5T567_LDORTC1DAC = 0x56, |
||||
RN5T567_LDORTC2DAC = 0x57, |
||||
|
||||
RN5T567_LDO1DAC_SLP = 0x58, |
||||
RN5T567_LDO2DAC_SLP = 0x59, |
||||
RN5T567_LDO3DAC_SLP = 0x5A, |
||||
RN5T567_LDO4DAC_SLP = 0x5B, |
||||
RN5T567_LDO5DAC_SLP = 0x5C, |
||||
|
||||
RN5T567_IOSEL = 0x90, |
||||
RN5T567_IOOUT = 0x91, |
||||
RN5T567_GPEDGE1 = 0x92, |
||||
RN5T567_EN_GPIR = 0x94, |
||||
RN5T567_IR_GPR = 0x95, |
||||
RN5T567_IR_GPF = 0x96, |
||||
RN5T567_MON_IOIN = 0x97, |
||||
RN5T567_GPLED_FUNC = 0x98, |
||||
RN5T567_INTPOL = 0x9C, |
||||
RN5T567_INTEN = 0x9D, |
||||
RN5T567_INTMON = 0x9E, |
||||
|
||||
RN5T567_PREVINDAC = 0xB0, |
||||
RN5T567_OVTEMP = 0xBC, |
||||
|
||||
RN5T567_NUM_OF_REGS = 0xBF, |
||||
}; |
||||
|
||||
#endif |
@ -0,0 +1,164 @@ |
||||
/*
|
||||
* Image manipulator for Vybrid SoCs |
||||
* |
||||
* Derived from vybridimage.c |
||||
* |
||||
* (C) Copyright 2016 DENX Software Engineering GmbH |
||||
* Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#include "imagetool.h" |
||||
#include <compiler.h> |
||||
#include <image.h> |
||||
|
||||
/*
|
||||
* NAND page 0 boot header |
||||
*/ |
||||
|
||||
struct nand_page_0_boot_header { |
||||
union { |
||||
uint32_t fcb[128]; |
||||
uint8_t fcb_bytes[512]; |
||||
}; /* 0x00000000 - 0x000001ff */ |
||||
uint8_t sw_ecc[512]; /* 0x00000200 - 0x000003ff */ |
||||
uint32_t padding[65280]; /* 0x00000400 - 0x0003ffff */ |
||||
uint8_t ivt_prefix[1024]; /* 0x00040000 - 0x000403ff */ |
||||
}; |
||||
|
||||
/* signature byte for a readable block */ |
||||
|
||||
static struct nand_page_0_boot_header vybridimage_header; |
||||
|
||||
static int vybridimage_check_image_types(uint8_t type) |
||||
{ |
||||
if (type == IH_TYPE_VYBRIDIMAGE) |
||||
return EXIT_SUCCESS; |
||||
return EXIT_FAILURE; |
||||
} |
||||
|
||||
static uint8_t vybridimage_sw_ecc(uint8_t byte) |
||||
{ |
||||
uint8_t bit0 = (byte & (1 << 0)) ? 1 : 0; |
||||
uint8_t bit1 = (byte & (1 << 1)) ? 1 : 0; |
||||
uint8_t bit2 = (byte & (1 << 2)) ? 1 : 0; |
||||
uint8_t bit3 = (byte & (1 << 3)) ? 1 : 0; |
||||
uint8_t bit4 = (byte & (1 << 4)) ? 1 : 0; |
||||
uint8_t bit5 = (byte & (1 << 5)) ? 1 : 0; |
||||
uint8_t bit6 = (byte & (1 << 6)) ? 1 : 0; |
||||
uint8_t bit7 = (byte & (1 << 7)) ? 1 : 0; |
||||
uint8_t res = 0; |
||||
|
||||
res |= ((bit6 ^ bit5 ^ bit3 ^ bit2) << 0); |
||||
res |= ((bit7 ^ bit5 ^ bit4 ^ bit2 ^ bit1) << 1); |
||||
res |= ((bit7 ^ bit6 ^ bit5 ^ bit1 ^ bit0) << 2); |
||||
res |= ((bit7 ^ bit4 ^ bit3 ^ bit0) << 3); |
||||
res |= ((bit6 ^ bit4 ^ bit3 ^ bit2 ^ bit1 ^ bit0) << 4); |
||||
|
||||
return res; |
||||
} |
||||
|
||||
static int vybridimage_verify_header(unsigned char *ptr, int image_size, |
||||
struct image_tool_params *params) |
||||
{ |
||||
struct nand_page_0_boot_header *hdr = |
||||
(struct nand_page_0_boot_header *)ptr; |
||||
int idx; |
||||
|
||||
if (hdr->fcb[1] != 0x46434220) |
||||
return -1; |
||||
if (hdr->fcb[2] != 1) |
||||
return -1; |
||||
if (hdr->fcb[7] != 64) |
||||
return -1; |
||||
if (hdr->fcb[14] != 6) |
||||
return -1; |
||||
if (hdr->fcb[30] != 0x0001ff00) |
||||
return -1; |
||||
if (hdr->fcb[43] != 1) |
||||
return -1; |
||||
if (hdr->fcb[54] != 0) |
||||
return -1; |
||||
if (hdr->fcb[55] != 8) |
||||
return -1; |
||||
|
||||
/* check software ECC */ |
||||
for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) { |
||||
uint8_t sw_ecc = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); |
||||
if (sw_ecc != hdr->sw_ecc[idx]) |
||||
return -1; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void vybridimage_set_header(void *ptr, struct stat *sbuf, int ifd, |
||||
struct image_tool_params *params) |
||||
{ |
||||
struct nand_page_0_boot_header *hdr = |
||||
(struct nand_page_0_boot_header *)ptr; |
||||
int idx; |
||||
|
||||
/* fill header with 0x00 for first 56 entries then 0xff */ |
||||
memset(&hdr->fcb[0], 0x0, 56*sizeof(uint32_t)); |
||||
memset(&hdr->fcb[56], 0xff, 72*sizeof(uint32_t)); |
||||
/* fill SW ecc and padding with 0xff */ |
||||
memset(&hdr->sw_ecc[0], 0xff, sizeof(hdr->sw_ecc)); |
||||
memset(&hdr->padding[0], 0xff, sizeof(hdr->padding)); |
||||
/* fill IVT prefix with 0x00 */ |
||||
memset(&hdr->ivt_prefix[0], 0x00, sizeof(hdr->ivt_prefix)); |
||||
|
||||
/* populate fcb */ |
||||
hdr->fcb[1] = 0x46434220; /* signature */ |
||||
hdr->fcb[2] = 0x00000001; /* version */ |
||||
hdr->fcb[5] = 2048; /* page size */ |
||||
hdr->fcb[6] = (2048+64); /* page + OOB size */ |
||||
hdr->fcb[7] = 64; /* pages per block */ |
||||
hdr->fcb[14] = 6; /* ECC mode 6 */ |
||||
hdr->fcb[26] = 128; /* fw address (0x40000) in 2K pages */ |
||||
hdr->fcb[27] = 128; /* fw address (0x40000) in 2K pages */ |
||||
hdr->fcb[30] = 0x0001ff00; /* DBBT search area start address */ |
||||
hdr->fcb[33] = 2048; /* BB marker physical offset */ |
||||
hdr->fcb[43] = 1; /* DISBBM */ |
||||
hdr->fcb[54] = 0; /* DISBB_Search */ |
||||
hdr->fcb[55] = 8; /* Bad block search limit */ |
||||
|
||||
/* compute software ECC */ |
||||
for (idx = 0; idx < sizeof(hdr->fcb_bytes); idx++) |
||||
hdr->sw_ecc[idx] = vybridimage_sw_ecc(hdr->fcb_bytes[idx]); |
||||
} |
||||
|
||||
static void vybridimage_print_hdr_field(struct nand_page_0_boot_header *hdr, |
||||
int idx) |
||||
{ |
||||
printf("header.fcb[%d] = %08x\n", idx, hdr->fcb[idx]); |
||||
} |
||||
|
||||
static void vybridimage_print_header(const void *ptr) |
||||
{ |
||||
struct nand_page_0_boot_header *hdr = |
||||
(struct nand_page_0_boot_header *)ptr; |
||||
int idx; |
||||
|
||||
for (idx = 0; idx < 56; idx++) |
||||
vybridimage_print_hdr_field(hdr, idx); |
||||
} |
||||
|
||||
/*
|
||||
* vybridimage parameters |
||||
*/ |
||||
U_BOOT_IMAGE_TYPE( |
||||
vybridimage, |
||||
"Vybrid Boot Image", |
||||
sizeof(vybridimage_header), |
||||
(void *)&vybridimage_header, |
||||
NULL, |
||||
vybridimage_verify_header, |
||||
vybridimage_print_header, |
||||
vybridimage_set_header, |
||||
NULL, |
||||
vybridimage_check_image_types, |
||||
NULL, |
||||
NULL |
||||
); |
Loading…
Reference in new issue