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@ -60,8 +60,6 @@ |
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"SDRAM_" #mnemonic, SDRAM_##mnemonic, data); \
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} while (0) |
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static inline void ppc4xx_ibm_ddr2_register_dump(void); |
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#if defined(CONFIG_SPD_EEPROM) |
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/*-----------------------------------------------------------------------------+
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@ -260,62 +258,19 @@ static void program_ecc_addr(unsigned long start_address, |
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unsigned long num_bytes, |
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unsigned long tlb_word2_i_value); |
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#endif |
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#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) |
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static void program_DQS_calibration(unsigned long *dimm_populated, |
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unsigned char *iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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unsigned char *iic0_dimm_addr, |
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unsigned long num_dimm_banks); |
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#ifdef HARD_CODED_DQS /* calibration test with hardvalues */ |
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static void test(void); |
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#else |
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static void DQS_calibration_process(void); |
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#endif |
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#endif |
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int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); |
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void dcbz_area(u32 start_address, u32 num_bytes); |
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static u32 mfdcr_any(u32 dcr) |
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{ |
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u32 val; |
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switch (dcr) { |
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case SDRAM_R0BAS + 0: |
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val = mfdcr(SDRAM_R0BAS + 0); |
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break; |
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case SDRAM_R0BAS + 1: |
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val = mfdcr(SDRAM_R0BAS + 1); |
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break; |
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case SDRAM_R0BAS + 2: |
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val = mfdcr(SDRAM_R0BAS + 2); |
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break; |
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case SDRAM_R0BAS + 3: |
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val = mfdcr(SDRAM_R0BAS + 3); |
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break; |
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default: |
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printf("DCR %d not defined in case statement!!!\n", dcr); |
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val = 0; /* just to satisfy the compiler */ |
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} |
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return val; |
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} |
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static void mtdcr_any(u32 dcr, u32 val) |
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{ |
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switch (dcr) { |
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case SDRAM_R0BAS + 0: |
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mtdcr(SDRAM_R0BAS + 0, val); |
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break; |
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case SDRAM_R0BAS + 1: |
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mtdcr(SDRAM_R0BAS + 1, val); |
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break; |
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case SDRAM_R0BAS + 2: |
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mtdcr(SDRAM_R0BAS + 2, val); |
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break; |
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case SDRAM_R0BAS + 3: |
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mtdcr(SDRAM_R0BAS + 3, val); |
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break; |
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default: |
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printf("DCR %d not defined in case statement!!!\n", dcr); |
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} |
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} |
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static unsigned char spd_read(uchar chip, uint addr) |
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{ |
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unsigned char data[2]; |
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@ -609,7 +564,11 @@ phys_size_t initdram(int board_type) |
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/*------------------------------------------------------------------
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* DQS calibration. |
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*-----------------------------------------------------------------*/ |
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#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) |
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DQS_autocalibration(); |
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#else |
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program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks); |
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#endif |
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#ifdef CONFIG_DDR_ECC |
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/*------------------------------------------------------------------
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@ -2329,18 +2288,6 @@ static unsigned long is_ecc_enabled(void) |
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return ecc; |
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} |
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static void blank_string(int size) |
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{ |
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int i; |
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for (i=0; i<size; i++) |
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putc('\b'); |
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for (i=0; i<size; i++) |
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putc(' '); |
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for (i=0; i<size; i++) |
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putc('\b'); |
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} |
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#ifdef CONFIG_DDR_ECC |
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/*-----------------------------------------------------------------------------+
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* program_ecc. |
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@ -2468,6 +2415,7 @@ static void program_ecc_addr(unsigned long start_address, |
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} |
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#endif |
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#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) |
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/*-----------------------------------------------------------------------------+
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* program_DQS_calibration. |
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*-----------------------------------------------------------------------------*/ |
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@ -3001,7 +2949,8 @@ static void test(void) |
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(ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK) |
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| ecc_temp); |
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} |
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#endif |
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#endif /* !HARD_CODED_DQS */ |
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#endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */ |
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#else /* CONFIG_SPD_EEPROM */ |
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@ -3104,9 +3053,12 @@ phys_size_t initdram(int board_type) |
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/* Set Delay Control Registers */ |
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mtsdram(SDRAM_DLCR, CFG_SDRAM0_DLCR); |
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#if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) |
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mtsdram(SDRAM_RDCC, CFG_SDRAM0_RDCC); |
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mtsdram(SDRAM_RQDC, CFG_SDRAM0_RQDC); |
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mtsdram(SDRAM_RFDC, CFG_SDRAM0_RFDC); |
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#endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ |
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/*
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* Enable Controller by SDRAM0_MCOPT2[DCEN] = 1: |
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@ -3115,18 +3067,98 @@ phys_size_t initdram(int board_type) |
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mfsdram(SDRAM_MCOPT2, val); |
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mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE); |
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#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) |
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
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/*------------------------------------------------------------------
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| DQS calibration. |
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+-----------------------------------------------------------------*/ |
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DQS_autocalibration(); |
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#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ |
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#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ |
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#if defined(CONFIG_DDR_ECC) |
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ecc_init(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20); |
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#endif /* defined(CONFIG_DDR_ECC) */ |
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ppc4xx_ibm_ddr2_register_dump(); |
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#if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) |
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/*
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* Clear potential errors resulting from auto-calibration. |
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* If not done, then we could get an interrupt later on when |
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* exceptions are enabled. |
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*/ |
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set_mcsr(get_mcsr()); |
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#endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ |
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#endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */ |
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return (CFG_MBYTES_SDRAM << 20); |
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} |
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#endif /* CONFIG_SPD_EEPROM */ |
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static inline void ppc4xx_ibm_ddr2_register_dump(void) |
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#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
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#if defined(CONFIG_440) |
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u32 mfdcr_any(u32 dcr) |
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{ |
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u32 val; |
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switch (dcr) { |
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case SDRAM_R0BAS + 0: |
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val = mfdcr(SDRAM_R0BAS + 0); |
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break; |
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case SDRAM_R0BAS + 1: |
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val = mfdcr(SDRAM_R0BAS + 1); |
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break; |
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case SDRAM_R0BAS + 2: |
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val = mfdcr(SDRAM_R0BAS + 2); |
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break; |
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case SDRAM_R0BAS + 3: |
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val = mfdcr(SDRAM_R0BAS + 3); |
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break; |
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default: |
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printf("DCR %d not defined in case statement!!!\n", dcr); |
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val = 0; /* just to satisfy the compiler */ |
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} |
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return val; |
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} |
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void mtdcr_any(u32 dcr, u32 val) |
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{ |
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switch (dcr) { |
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case SDRAM_R0BAS + 0: |
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mtdcr(SDRAM_R0BAS + 0, val); |
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break; |
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case SDRAM_R0BAS + 1: |
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mtdcr(SDRAM_R0BAS + 1, val); |
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break; |
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case SDRAM_R0BAS + 2: |
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mtdcr(SDRAM_R0BAS + 2, val); |
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break; |
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case SDRAM_R0BAS + 3: |
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mtdcr(SDRAM_R0BAS + 3, val); |
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break; |
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default: |
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printf("DCR %d not defined in case statement!!!\n", dcr); |
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} |
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} |
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#endif /* defined(CONFIG_440) */ |
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void blank_string(int size) |
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{ |
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int i; |
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for (i = 0; i < size; i++) |
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putc('\b'); |
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for (i = 0; i < size; i++) |
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putc(' '); |
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for (i = 0; i < size; i++) |
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putc('\b'); |
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} |
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#endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ |
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inline void ppc4xx_ibm_ddr2_register_dump(void) |
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{ |
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#if defined(DEBUG) |
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printf("\nPPC4xx IBM DDR2 Register Dump:\n"); |
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