Faraday FTSDC010 is a MMC/SD host controller. Although there is already a driver in current u-boot release, which is modified from eSHDC and contributed by Andes Tech. Its performance is too terrible on Faraday A36x SoC platforms, so I turn to implement this new version of driver which is 10+ times faster than the old one. It's carefully designed to be compatible with Andes chips, so it should be safe to replace it. Signed-off-by: Kuo-Jung Su <dantesu@faraday-tech.com> CC: Andy Fleming <afleming@gmail.com> Signed-off-by: Andy Fleming <afleming@freescale.com>master
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/*
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* Copyright (C) 2011 Andes Technology Corporation |
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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#include <config.h> |
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#include <common.h> |
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#include <mmc.h> |
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#include <asm/io.h> |
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#include <faraday/ftsdc010.h> |
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|
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/*
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* supported mmc hosts |
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* setting the number CONFIG_FTSDC010_NUMBER in your configuration file. |
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*/ |
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static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER]; |
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static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER]; |
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static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index) |
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{ |
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return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index; |
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} |
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#ifdef DEBUG |
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static void ftsdc010_dump_reg(struct mmc_host *host) |
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{ |
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debug("cmd: %08x\n", readl(&host->reg->cmd)); |
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debug("argu: %08x\n", readl(&host->reg->argu)); |
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debug("rsp0: %08x\n", readl(&host->reg->rsp0)); |
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debug("rsp1: %08x\n", readl(&host->reg->rsp1)); |
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debug("rsp2: %08x\n", readl(&host->reg->rsp2)); |
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debug("rsp3: %08x\n", readl(&host->reg->rsp3)); |
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debug("rsp_cmd: %08x\n", readl(&host->reg->rsp_cmd)); |
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debug("dcr: %08x\n", readl(&host->reg->dcr)); |
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debug("dtr: %08x\n", readl(&host->reg->dtr)); |
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debug("dlr: %08x\n", readl(&host->reg->dlr)); |
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debug("status: %08x\n", readl(&host->reg->status)); |
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debug("clr: %08x\n", readl(&host->reg->clr)); |
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debug("int_mask: %08x\n", readl(&host->reg->int_mask)); |
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debug("pcr: %08x\n", readl(&host->reg->pcr)); |
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debug("ccr: %08x\n", readl(&host->reg->ccr)); |
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debug("bwr: %08x\n", readl(&host->reg->bwr)); |
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debug("dwr: %08x\n", readl(&host->reg->dwr)); |
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debug("feature: %08x\n", readl(&host->reg->feature)); |
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debug("rev: %08x\n", readl(&host->reg->rev)); |
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} |
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#endif |
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static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask) |
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{ |
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unsigned int newmask; |
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newmask = readl(®->int_mask); |
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newmask |= imask; |
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writel(newmask, ®->int_mask); |
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return newmask; |
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} |
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static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size) |
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{ |
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unsigned int fifo; |
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unsigned int fifo_words; |
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unsigned int *ptr; |
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unsigned int status; |
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unsigned int retry = 0; |
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/* get_data_buffer */ |
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ptr = (unsigned int *)buf; |
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while (size) { |
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status = readl(&host->reg->status); |
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debug("%s: size: %08x\n", __func__, size); |
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if (status & FTSDC010_STATUS_FIFO_ORUN) { |
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debug("%s: FIFO OVERRUN: sta: %08x\n", |
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__func__, status); |
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fifo = host->fifo_len > size ? |
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size : host->fifo_len; |
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size -= fifo; |
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fifo_words = fifo >> 2; |
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while (fifo_words--) |
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*ptr++ = readl(&host->reg->dwr); |
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/*
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* for adding some delays for SD card to put |
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* data into FIFO again |
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*/ |
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udelay(4*FTSDC010_DELAY_UNIT); |
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#ifdef CONFIG_FTSDC010_SDIO |
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/* sdio allow non-power-of-2 blksz */ |
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if (fifo & 3) { |
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unsigned int n = fifo & 3; |
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unsigned int data = readl(&host->reg->dwr); |
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unsigned char *p = (unsigned char *)ptr; |
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while (n--) { |
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*p++ = data; |
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data >>= 8; |
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} |
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} |
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#endif |
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} else { |
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udelay(1); |
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if (++retry >= FTSDC010_PIO_RETRY) { |
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debug("%s: PIO_RETRY timeout\n", __func__); |
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return; |
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} |
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} |
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} |
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} |
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static void ftsdc010_pio_write(struct mmc_host *host, const char *buf, |
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unsigned int size) |
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{ |
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unsigned int fifo; |
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unsigned int *ptr; |
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unsigned int status; |
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unsigned int retry = 0; |
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/* get data buffer */ |
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ptr = (unsigned int *)buf; |
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while (size) { |
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status = readl(&host->reg->status); |
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if (status & FTSDC010_STATUS_FIFO_URUN) { |
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fifo = host->fifo_len > size ? |
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size : host->fifo_len; |
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size -= fifo; |
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fifo = (fifo + 3) >> 2; |
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while (fifo--) { |
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writel(*ptr, &host->reg->dwr); |
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ptr++; |
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} |
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} else { |
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udelay(1); |
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if (++retry >= FTSDC010_PIO_RETRY) { |
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debug("%s: PIO_RETRY timeout\n", __func__); |
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return; |
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} |
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} |
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} |
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} |
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static int ftsdc010_check_rsp(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct mmc_host *host = mmc->priv; |
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unsigned int sta, clear; |
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sta = readl(&host->reg->status); |
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debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx); |
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/* check RSP TIMEOUT or FAIL */ |
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if (sta & FTSDC010_STATUS_RSP_TIMEOUT) { |
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/* RSP TIMEOUT */ |
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debug("%s: RSP timeout: sta: %08x\n", __func__, sta); |
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clear |= FTSDC010_CLR_RSP_TIMEOUT; |
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writel(clear, &host->reg->clr); |
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return TIMEOUT; |
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} else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) { |
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/* clear response fail bit */ |
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debug("%s: RSP CRC FAIL: sta: %08x\n", __func__, sta); |
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clear |= FTSDC010_CLR_RSP_CRC_FAIL; |
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writel(clear, &host->reg->clr); |
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return COMM_ERR; |
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} else if (sta & FTSDC010_STATUS_RSP_CRC_OK) { |
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/* clear response CRC OK bit */ |
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clear |= FTSDC010_CLR_RSP_CRC_OK; |
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} |
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writel(clear, &host->reg->clr); |
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return 0; |
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} |
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static int ftsdc010_check_data(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct mmc_host *host = mmc->priv; |
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unsigned int sta, clear; |
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sta = readl(&host->reg->status); |
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debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx); |
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/* check DATA TIMEOUT or FAIL */ |
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if (data) { |
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/* Transfer Complete */ |
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if (sta & FTSDC010_STATUS_DATA_END) |
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clear |= FTSDC010_STATUS_DATA_END; |
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/* Data CRC_OK */ |
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if (sta & FTSDC010_STATUS_DATA_CRC_OK) |
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clear |= FTSDC010_STATUS_DATA_CRC_OK; |
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/* DATA TIMEOUT or DATA CRC FAIL */ |
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if (sta & FTSDC010_STATUS_DATA_TIMEOUT) { |
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/* DATA TIMEOUT */ |
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debug("%s: DATA TIMEOUT: sta: %08x\n", __func__, sta); |
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clear |= FTSDC010_STATUS_DATA_TIMEOUT; |
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writel(clear, &host->reg->clr); |
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return TIMEOUT; |
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} else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) { |
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/* DATA CRC FAIL */ |
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debug("%s: DATA CRC FAIL: sta: %08x\n", __func__, sta); |
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clear |= FTSDC010_STATUS_DATA_CRC_FAIL; |
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writel(clear, &host->reg->clr); |
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return COMM_ERR; |
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} |
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writel(clear, &host->reg->clr); |
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} |
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return 0; |
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} |
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static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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struct mmc_host *host = mmc->priv; |
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#ifdef CONFIG_FTSDC010_SDIO |
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unsigned int scon; |
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#endif |
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unsigned int ccon; |
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unsigned int mask, tmpmask; |
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unsigned int ret; |
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unsigned int sta, i; |
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ret = 0; |
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if (data) |
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mask = FTSDC010_INT_MASK_RSP_TIMEOUT; |
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else if (cmd->resp_type & MMC_RSP_PRESENT) |
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mask = FTSDC010_INT_MASK_RSP_TIMEOUT; |
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else |
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mask = FTSDC010_INT_MASK_CMD_SEND; |
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/* write argu reg */ |
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debug("%s: argu: %08x\n", __func__, host->reg->argu); |
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writel(cmd->cmdarg, &host->reg->argu); |
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/* setup commnad */ |
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ccon = FTSDC010_CMD_IDX(cmd->cmdidx); |
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/* setup command flags */ |
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ccon |= FTSDC010_CMD_CMD_EN; |
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/*
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* This hardware didn't support specific commands for mapping |
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* MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it. |
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*/ |
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if (cmd->resp_type & MMC_RSP_PRESENT) { |
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ccon |= FTSDC010_CMD_NEED_RSP; |
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mask |= FTSDC010_INT_MASK_RSP_CRC_OK | |
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FTSDC010_INT_MASK_RSP_CRC_FAIL; |
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} |
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if (cmd->resp_type & MMC_RSP_136) |
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ccon |= FTSDC010_CMD_LONG_RSP; |
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/* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */ |
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if (host->last_opcode == MMC_CMD_APP_CMD) |
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ccon |= FTSDC010_CMD_APP_CMD; |
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#ifdef CONFIG_FTSDC010_SDIO |
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scon = readl(&host->reg->sdio_ctrl1); |
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if (host->card_type == MMC_TYPE_SDIO) |
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scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE; |
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else |
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scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE; |
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writel(scon, &host->reg->sdio_ctrl1); |
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#endif |
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/* record last opcode for specifing the command type to hardware */ |
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host->last_opcode = cmd->cmdidx; |
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/* write int_mask reg */ |
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tmpmask = readl(&host->reg->int_mask); |
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tmpmask |= mask; |
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writel(tmpmask, &host->reg->int_mask); |
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/* write cmd reg */ |
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debug("%s: ccon: %08x\n", __func__, ccon); |
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writel(ccon, &host->reg->cmd); |
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/* check CMD_SEND */ |
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for (i = 0; i < FTSDC010_CMD_RETRY; i++) { |
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/*
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* If we read status register too fast |
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* will lead hardware error and the RSP_TIMEOUT |
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* flag will be raised incorrectly. |
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*/ |
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udelay(16*FTSDC010_DELAY_UNIT); |
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sta = readl(&host->reg->status); |
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/* Command Complete */ |
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/*
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* Note: |
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* Do not clear FTSDC010_CLR_CMD_SEND flag. |
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* (by writing FTSDC010_CLR_CMD_SEND bit to clear register) |
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* It will make the driver becomes very slow. |
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* If the operation hasn't been finished, hardware will |
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* clear this bit automatically. |
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* In origin, the driver will clear this flag if there is |
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* no data need to be read. |
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*/ |
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if (sta & FTSDC010_STATUS_CMD_SEND) |
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break; |
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} |
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if (i > FTSDC010_CMD_RETRY) { |
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printf("%s: send command timeout\n", __func__); |
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return TIMEOUT; |
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} |
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/* check rsp status */ |
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ret = ftsdc010_check_rsp(mmc, cmd, data); |
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if (ret) |
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return ret; |
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/* read response if we have RSP_OK */ |
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if (ccon & FTSDC010_CMD_LONG_RSP) { |
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cmd->response[0] = readl(&host->reg->rsp3); |
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cmd->response[1] = readl(&host->reg->rsp2); |
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cmd->response[2] = readl(&host->reg->rsp1); |
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cmd->response[3] = readl(&host->reg->rsp0); |
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} else { |
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cmd->response[0] = readl(&host->reg->rsp0); |
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} |
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/* read/write data */ |
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if (data && (data->flags & MMC_DATA_READ)) { |
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ftsdc010_pio_read(host, data->dest, |
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data->blocksize * data->blocks); |
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} else if (data && (data->flags & MMC_DATA_WRITE)) { |
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ftsdc010_pio_write(host, data->src, |
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data->blocksize * data->blocks); |
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} |
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/* check data status */ |
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if (data) { |
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ret = ftsdc010_check_data(mmc, cmd, data); |
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if (ret) |
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return ret; |
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} |
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udelay(FTSDC010_DELAY_UNIT); |
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return ret; |
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} |
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static unsigned int cal_blksz(unsigned int blksz) |
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{ |
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unsigned int blksztwo = 0; |
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while (blksz >>= 1) |
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blksztwo++; |
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return blksztwo; |
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} |
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static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data) |
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{ |
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struct mmc_host *host = mmc->priv; |
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unsigned int dcon, newmask; |
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/* configure data transfer paramter */ |
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if (!data) |
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return 0; |
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if (((data->blocksize - 1) & data->blocksize) != 0) { |
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printf("%s: can't do non-power-of 2 sized block transfers" |
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" (blksz %d)\n", __func__, data->blocksize); |
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return -1; |
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} |
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/*
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* We cannot deal with unaligned blocks with more than |
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* one block being transfered. |
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*/ |
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if ((data->blocksize <= 2) && (data->blocks > 1)) { |
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printf("%s: can't do non-word sized block transfers" |
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" (blksz %d)\n", __func__, data->blocksize); |
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return -1; |
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} |
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/* data length */ |
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dcon = data->blocksize * data->blocks; |
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writel(dcon, &host->reg->dlr); |
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/* write data control */ |
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dcon = cal_blksz(data->blocksize); |
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/* add to IMASK register */ |
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newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT); |
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/*
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* enable UNDERRUN will trigger interrupt immediatedly |
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* So setup it when rsp is received successfully |
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*/ |
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if (data->flags & MMC_DATA_WRITE) { |
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dcon |= FTSDC010_DCR_DATA_WRITE; |
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} else { |
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dcon &= ~FTSDC010_DCR_DATA_WRITE; |
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newmask |= FTSDC010_STATUS_FIFO_ORUN; |
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} |
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enable_imask(host->reg, newmask); |
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#ifdef CONFIG_FTSDC010_SDIO |
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/* always reset fifo since last transfer may fail */ |
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dcon |= FTSDC010_DCR_FIFO_RST; |
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if (data->blocks > 1) |
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dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE; |
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#endif |
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/* enable data transfer which will be pended until cmd is send */ |
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dcon |= FTSDC010_DCR_DATA_EN; |
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writel(dcon, &host->reg->dcr); |
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return 0; |
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} |
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static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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int ret; |
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if (data) { |
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ret = ftsdc010_setup_data(mmc, data); |
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if (ret) { |
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printf("%s: setup data error\n", __func__); |
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return -1; |
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} |
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if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) { |
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printf("%s: data is both direction\n", __func__); |
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return -1; |
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} |
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} |
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/* Send command */ |
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ret = ftsdc010_send_cmd(mmc, cmd, data); |
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return ret; |
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} |
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static int ftsdc010_card_detect(struct mmc *mmc) |
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{ |
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struct mmc_host *host = mmc->priv; |
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unsigned int sta; |
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sta = readl(&host->reg->status); |
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debug("%s: card status: %08x\n", __func__, sta); |
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return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1; |
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} |
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static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, |
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struct mmc_data *data) |
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{ |
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int ret; |
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if (ftsdc010_card_detect(mmc) == 0) { |
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printf("%s: no medium present\n", __func__); |
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return -1; |
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} else { |
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ret = ftsdc010_send_request(mmc, cmd, data); |
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return ret; |
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} |
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} |
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static void ftsdc010_set_clk(struct mmc *mmc) |
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{ |
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struct mmc_host *host = mmc->priv; |
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unsigned char clk_div; |
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unsigned int real_rate; |
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unsigned int clock; |
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debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock); |
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clock = readl(&host->reg->ccr); |
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if (mmc->clock == 0) { |
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real_rate = 0; |
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clock |= FTSDC010_CCR_CLK_DIS; |
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} else { |
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debug("%s, mmc->clock: %08x, origin clock: %08x\n", |
||||
__func__, mmc->clock, clock); |
||||
|
||||
for (clk_div = 0; clk_div <= 127; clk_div++) { |
||||
real_rate = (CONFIG_SYS_CLK_FREQ / 2) / |
||||
(2 * (clk_div + 1)); |
||||
|
||||
if (real_rate <= mmc->clock) |
||||
break; |
||||
} |
||||
|
||||
debug("%s: computed real_rate: %x, clk_div: %x\n", |
||||
__func__, real_rate, clk_div); |
||||
|
||||
if (clk_div > 127) |
||||
debug("%s: no match clock rate, %x\n", |
||||
__func__, mmc->clock); |
||||
|
||||
clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) | |
||||
FTSDC010_CCR_CLK_DIV(clk_div); |
||||
|
||||
clock &= ~FTSDC010_CCR_CLK_DIS; |
||||
} |
||||
|
||||
debug("%s, set clock: %08x\n", __func__, clock); |
||||
writel(clock, &host->reg->ccr); |
||||
} |
||||
|
||||
static void ftsdc010_set_ios(struct mmc *mmc) |
||||
{ |
||||
struct mmc_host *host = mmc->priv; |
||||
unsigned int power; |
||||
unsigned long val; |
||||
unsigned int bus_width; |
||||
|
||||
debug("%s: bus_width: %x, clock: %d\n", |
||||
__func__, mmc->bus_width, mmc->clock); |
||||
|
||||
/* set pcr: power on */ |
||||
power = readl(&host->reg->pcr); |
||||
power |= FTSDC010_PCR_POWER_ON; |
||||
writel(power, &host->reg->pcr); |
||||
|
||||
if (mmc->clock) |
||||
ftsdc010_set_clk(mmc); |
||||
|
||||
/* set bwr: bus width reg */ |
||||
bus_width = readl(&host->reg->bwr); |
||||
bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS | |
||||
FTSDC010_BWR_SINGLE_BUS); |
||||
|
||||
if (mmc->bus_width == 8) |
||||
bus_width |= FTSDC010_BWR_WIDE_8_BUS; |
||||
else if (mmc->bus_width == 4) |
||||
bus_width |= FTSDC010_BWR_WIDE_4_BUS; |
||||
else |
||||
bus_width |= FTSDC010_BWR_SINGLE_BUS; |
||||
|
||||
writel(bus_width, &host->reg->bwr); |
||||
|
||||
/* set fifo depth */ |
||||
val = readl(&host->reg->feature); |
||||
host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */ |
||||
|
||||
/* set data timeout register */ |
||||
val = -1; |
||||
writel(val, &host->reg->dtr); |
||||
} |
||||
|
||||
static void ftsdc010_reset(struct mmc_host *host) |
||||
{ |
||||
unsigned int timeout; |
||||
unsigned int sta; |
||||
|
||||
/* Do SDC_RST: Software reset for all register */ |
||||
writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd); |
||||
|
||||
host->clock = 0; |
||||
|
||||
/* this hardware has no reset finish flag to read */ |
||||
/* wait 100ms maximum */ |
||||
timeout = 100; |
||||
|
||||
/* hw clears the bit when it's done */ |
||||
while (readl(&host->reg->dtr) != 0) { |
||||
if (timeout == 0) { |
||||
printf("%s: reset timeout error\n", __func__); |
||||
return; |
||||
} |
||||
timeout--; |
||||
udelay(10*FTSDC010_DELAY_UNIT); |
||||
} |
||||
|
||||
sta = readl(&host->reg->status); |
||||
if (sta & FTSDC010_STATUS_CARD_CHANGE) |
||||
writel(FTSDC010_CLR_CARD_CHANGE, &host->reg->clr); |
||||
} |
||||
|
||||
static int ftsdc010_core_init(struct mmc *mmc) |
||||
{ |
||||
struct mmc_host *host = mmc->priv; |
||||
unsigned int mask; |
||||
unsigned int major, minor, revision; |
||||
|
||||
/* get hardware version */ |
||||
host->version = readl(&host->reg->rev); |
||||
|
||||
major = FTSDC010_REV_MAJOR(host->version); |
||||
minor = FTSDC010_REV_MINOR(host->version); |
||||
revision = FTSDC010_REV_REVISION(host->version); |
||||
|
||||
printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision); |
||||
|
||||
/* Interrupt MASK register init - mask all */ |
||||
writel(0x0, &host->reg->int_mask); |
||||
|
||||
mask = FTSDC010_INT_MASK_CMD_SEND | |
||||
FTSDC010_INT_MASK_DATA_END | |
||||
FTSDC010_INT_MASK_CARD_CHANGE; |
||||
#ifdef CONFIG_FTSDC010_SDIO |
||||
mask |= FTSDC010_INT_MASK_CP_READY | |
||||
FTSDC010_INT_MASK_CP_BUF_READY | |
||||
FTSDC010_INT_MASK_PLAIN_TEXT_READY | |
||||
FTSDC010_INT_MASK_SDIO_IRPT; |
||||
#endif |
||||
|
||||
writel(mask, &host->reg->int_mask); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int ftsdc010_mmc_init(int dev_index) |
||||
{ |
||||
struct mmc *mmc; |
||||
struct mmc_host *host; |
||||
|
||||
mmc = &ftsdc010_dev[dev_index]; |
||||
|
||||
sprintf(mmc->name, "FTSDC010 SD/MMC"); |
||||
mmc->priv = &ftsdc010_host[dev_index]; |
||||
mmc->send_cmd = ftsdc010_request; |
||||
mmc->set_ios = ftsdc010_set_ios; |
||||
mmc->init = ftsdc010_core_init; |
||||
mmc->getcd = NULL; |
||||
mmc->getwp = NULL; |
||||
|
||||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
||||
|
||||
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
||||
|
||||
mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128); |
||||
mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2; |
||||
|
||||
ftsdc010_host[dev_index].clock = 0; |
||||
ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index); |
||||
mmc_register(mmc); |
||||
|
||||
/* reset mmc */ |
||||
host = (struct mmc_host *)mmc->priv; |
||||
ftsdc010_reset(host); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,377 @@ |
||||
/*
|
||||
* Faraday MMC/SD Host Controller |
||||
* |
||||
* (C) Copyright 2010 Faraday Technology |
||||
* Dante Su <dantesu@faraday-tech.com> |
||||
* |
||||
* This file is released under the terms of GPL v2 and any later version. |
||||
* See the file COPYING in the root directory of the source tree for details. |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <malloc.h> |
||||
#include <part.h> |
||||
#include <mmc.h> |
||||
|
||||
#include <asm/io.h> |
||||
#include <asm/errno.h> |
||||
#include <asm/byteorder.h> |
||||
#include <faraday/ftsdc010.h> |
||||
|
||||
#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 4) /* 250 ms */ |
||||
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */ |
||||
|
||||
struct ftsdc010_chip { |
||||
void __iomem *regs; |
||||
uint32_t wprot; /* write protected (locked) */ |
||||
uint32_t rate; /* actual SD clock in Hz */ |
||||
uint32_t sclk; /* FTSDC010 source clock in Hz */ |
||||
uint32_t fifo; /* fifo depth in bytes */ |
||||
uint32_t acmd; |
||||
}; |
||||
|
||||
static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) |
||||
{ |
||||
struct ftsdc010_chip *chip = mmc->priv; |
||||
struct ftsdc010_mmc __iomem *regs = chip->regs; |
||||
int ret = TIMEOUT; |
||||
uint32_t ts, st; |
||||
uint32_t cmd = FTSDC010_CMD_IDX(mmc_cmd->cmdidx); |
||||
uint32_t arg = mmc_cmd->cmdarg; |
||||
uint32_t flags = mmc_cmd->resp_type; |
||||
|
||||
cmd |= FTSDC010_CMD_CMD_EN; |
||||
|
||||
if (chip->acmd) { |
||||
cmd |= FTSDC010_CMD_APP_CMD; |
||||
chip->acmd = 0; |
||||
} |
||||
|
||||
if (flags & MMC_RSP_PRESENT) |
||||
cmd |= FTSDC010_CMD_NEED_RSP; |
||||
|
||||
if (flags & MMC_RSP_136) |
||||
cmd |= FTSDC010_CMD_LONG_RSP; |
||||
|
||||
writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND, |
||||
®s->clr); |
||||
writel(arg, ®s->argu); |
||||
writel(cmd, ®s->cmd); |
||||
|
||||
if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) { |
||||
for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
||||
if (readl(®s->status) & FTSDC010_STATUS_CMD_SEND) { |
||||
writel(FTSDC010_STATUS_CMD_SEND, ®s->clr); |
||||
ret = 0; |
||||
break; |
||||
} |
||||
} |
||||
} else { |
||||
st = 0; |
||||
for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
||||
st = readl(®s->status); |
||||
writel(st & FTSDC010_STATUS_RSP_MASK, ®s->clr); |
||||
if (st & FTSDC010_STATUS_RSP_MASK) |
||||
break; |
||||
} |
||||
if (st & FTSDC010_STATUS_RSP_CRC_OK) { |
||||
if (flags & MMC_RSP_136) { |
||||
mmc_cmd->response[0] = readl(®s->rsp3); |
||||
mmc_cmd->response[1] = readl(®s->rsp2); |
||||
mmc_cmd->response[2] = readl(®s->rsp1); |
||||
mmc_cmd->response[3] = readl(®s->rsp0); |
||||
} else { |
||||
mmc_cmd->response[0] = readl(®s->rsp0); |
||||
} |
||||
ret = 0; |
||||
} else { |
||||
debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n", |
||||
mmc_cmd->cmdidx, st); |
||||
} |
||||
} |
||||
|
||||
if (ret) { |
||||
debug("ftsdc010: cmd timeout (op code=%d)\n", |
||||
mmc_cmd->cmdidx); |
||||
} else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) { |
||||
chip->acmd = 1; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate) |
||||
{ |
||||
struct ftsdc010_chip *chip = mmc->priv; |
||||
struct ftsdc010_mmc __iomem *regs = chip->regs; |
||||
uint32_t div; |
||||
|
||||
for (div = 0; div < 0x7f; ++div) { |
||||
if (rate >= chip->sclk / (2 * (div + 1))) |
||||
break; |
||||
} |
||||
chip->rate = chip->sclk / (2 * (div + 1)); |
||||
|
||||
writel(FTSDC010_CCR_CLK_DIV(div), ®s->ccr); |
||||
|
||||
if (IS_SD(mmc)) { |
||||
setbits_le32(®s->ccr, FTSDC010_CCR_CLK_SD); |
||||
|
||||
if (chip->rate > 25000000) |
||||
setbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); |
||||
else |
||||
clrbits_le32(®s->ccr, FTSDC010_CCR_CLK_HISPD); |
||||
} |
||||
} |
||||
|
||||
static inline int ftsdc010_is_ro(struct mmc *mmc) |
||||
{ |
||||
struct ftsdc010_chip *chip = mmc->priv; |
||||
const uint8_t *csd = (const uint8_t *)mmc->csd; |
||||
|
||||
return chip->wprot || (csd[1] & 0x30); |
||||
} |
||||
|
||||
static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask) |
||||
{ |
||||
int ret = TIMEOUT; |
||||
uint32_t st, ts; |
||||
|
||||
for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) { |
||||
st = readl(®s->status); |
||||
if (!(st & mask)) |
||||
continue; |
||||
writel(st & mask, ®s->clr); |
||||
ret = 0; |
||||
break; |
||||
} |
||||
|
||||
if (ret) |
||||
debug("ftsdc010: wait st(0x%x) timeout\n", mask); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
/*
|
||||
* u-boot mmc api |
||||
*/ |
||||
|
||||
static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd, |
||||
struct mmc_data *data) |
||||
{ |
||||
int ret = UNUSABLE_ERR; |
||||
uint32_t len = 0; |
||||
struct ftsdc010_chip *chip = mmc->priv; |
||||
struct ftsdc010_mmc __iomem *regs = chip->regs; |
||||
|
||||
if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) { |
||||
printf("ftsdc010: the card is write protected!\n"); |
||||
return ret; |
||||
} |
||||
|
||||
if (data) { |
||||
uint32_t dcr; |
||||
|
||||
len = data->blocksize * data->blocks; |
||||
|
||||
/* 1. data disable + fifo reset */ |
||||
writel(FTSDC010_DCR_FIFO_RST, ®s->dcr); |
||||
|
||||
/* 2. clear status register */ |
||||
writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN |
||||
| FTSDC010_STATUS_FIFO_ORUN, ®s->clr); |
||||
|
||||
/* 3. data timeout (1 sec) */ |
||||
writel(chip->rate, ®s->dtr); |
||||
|
||||
/* 4. data length (bytes) */ |
||||
writel(len, ®s->dlr); |
||||
|
||||
/* 5. data enable */ |
||||
dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN; |
||||
if (data->flags & MMC_DATA_WRITE) |
||||
dcr |= FTSDC010_DCR_DATA_WRITE; |
||||
writel(dcr, ®s->dcr); |
||||
} |
||||
|
||||
ret = ftsdc010_send_cmd(mmc, cmd); |
||||
if (ret) { |
||||
printf("ftsdc010: CMD%d failed\n", cmd->cmdidx); |
||||
return ret; |
||||
} |
||||
|
||||
if (!data) |
||||
return ret; |
||||
|
||||
if (data->flags & MMC_DATA_WRITE) { |
||||
const uint8_t *buf = (const uint8_t *)data->src; |
||||
|
||||
while (len > 0) { |
||||
int wlen; |
||||
|
||||
/* wait for tx ready */ |
||||
ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN); |
||||
if (ret) |
||||
break; |
||||
|
||||
/* write bytes to ftsdc010 */ |
||||
for (wlen = 0; wlen < len && wlen < chip->fifo; ) { |
||||
writel(*(uint32_t *)buf, ®s->dwr); |
||||
buf += 4; |
||||
wlen += 4; |
||||
} |
||||
|
||||
len -= wlen; |
||||
} |
||||
|
||||
} else { |
||||
uint8_t *buf = (uint8_t *)data->dest; |
||||
|
||||
while (len > 0) { |
||||
int rlen; |
||||
|
||||
/* wait for rx ready */ |
||||
ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN); |
||||
if (ret) |
||||
break; |
||||
|
||||
/* fetch bytes from ftsdc010 */ |
||||
for (rlen = 0; rlen < len && rlen < chip->fifo; ) { |
||||
*(uint32_t *)buf = readl(®s->dwr); |
||||
buf += 4; |
||||
rlen += 4; |
||||
} |
||||
|
||||
len -= rlen; |
||||
} |
||||
|
||||
} |
||||
|
||||
if (!ret) { |
||||
ret = ftsdc010_wait(regs, |
||||
FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_ERROR); |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void ftsdc010_set_ios(struct mmc *mmc) |
||||
{ |
||||
struct ftsdc010_chip *chip = mmc->priv; |
||||
struct ftsdc010_mmc __iomem *regs = chip->regs; |
||||
|
||||
ftsdc010_clkset(mmc, mmc->clock); |
||||
|
||||
clrbits_le32(®s->bwr, FTSDC010_BWR_MODE_MASK); |
||||
switch (mmc->bus_width) { |
||||
case 4: |
||||
setbits_le32(®s->bwr, FTSDC010_BWR_MODE_4BIT); |
||||
break; |
||||
case 8: |
||||
setbits_le32(®s->bwr, FTSDC010_BWR_MODE_8BIT); |
||||
break; |
||||
default: |
||||
setbits_le32(®s->bwr, FTSDC010_BWR_MODE_1BIT); |
||||
break; |
||||
} |
||||
} |
||||
|
||||
static int ftsdc010_init(struct mmc *mmc) |
||||
{ |
||||
struct ftsdc010_chip *chip = mmc->priv; |
||||
struct ftsdc010_mmc __iomem *regs = chip->regs; |
||||
uint32_t ts; |
||||
|
||||
if (readl(®s->status) & FTSDC010_STATUS_CARD_DETECT) |
||||
return NO_CARD_ERR; |
||||
|
||||
if (readl(®s->status) & FTSDC010_STATUS_WRITE_PROT) { |
||||
printf("ftsdc010: write protected\n"); |
||||
chip->wprot = 1; |
||||
} |
||||
|
||||
chip->fifo = (readl(®s->feature) & 0xff) << 2; |
||||
|
||||
/* 1. chip reset */ |
||||
writel(FTSDC010_CMD_SDC_RST, ®s->cmd); |
||||
for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) { |
||||
if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) |
||||
continue; |
||||
break; |
||||
} |
||||
if (readl(®s->cmd) & FTSDC010_CMD_SDC_RST) { |
||||
printf("ftsdc010: reset failed\n"); |
||||
return UNUSABLE_ERR; |
||||
} |
||||
|
||||
/* 2. enter low speed mode (400k card detection) */ |
||||
ftsdc010_clkset(mmc, 400000); |
||||
|
||||
/* 3. interrupt disabled */ |
||||
writel(0, ®s->int_mask); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int ftsdc010_mmc_init(int devid) |
||||
{ |
||||
struct mmc *mmc; |
||||
struct ftsdc010_chip *chip; |
||||
struct ftsdc010_mmc __iomem *regs; |
||||
#ifdef CONFIG_FTSDC010_BASE_LIST |
||||
uint32_t base_list[] = CONFIG_FTSDC010_BASE_LIST; |
||||
|
||||
if (devid < 0 || devid >= ARRAY_SIZE(base_list)) |
||||
return -1; |
||||
regs = (void __iomem *)base_list[devid]; |
||||
#else |
||||
regs = (void __iomem *)(CONFIG_FTSDC010_BASE + (devid << 20)); |
||||
#endif |
||||
|
||||
mmc = malloc(sizeof(struct mmc)); |
||||
if (!mmc) |
||||
return -ENOMEM; |
||||
memset(mmc, 0, sizeof(struct mmc)); |
||||
|
||||
chip = malloc(sizeof(struct ftsdc010_chip)); |
||||
if (!chip) { |
||||
free(mmc); |
||||
return -ENOMEM; |
||||
} |
||||
memset(chip, 0, sizeof(struct ftsdc010_chip)); |
||||
|
||||
chip->regs = regs; |
||||
mmc->priv = chip; |
||||
|
||||
sprintf(mmc->name, "ftsdc010"); |
||||
mmc->send_cmd = ftsdc010_request; |
||||
mmc->set_ios = ftsdc010_set_ios; |
||||
mmc->init = ftsdc010_init; |
||||
|
||||
mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz; |
||||
switch (readl(®s->bwr) & FTSDC010_BWR_CAPS_MASK) { |
||||
case FTSDC010_BWR_CAPS_4BIT: |
||||
mmc->host_caps |= MMC_MODE_4BIT; |
||||
break; |
||||
case FTSDC010_BWR_CAPS_8BIT: |
||||
mmc->host_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
#ifdef CONFIG_SYS_CLK_FREQ |
||||
chip->sclk = CONFIG_SYS_CLK_FREQ; |
||||
#else |
||||
chip->sclk = clk_get_rate("SDC"); |
||||
#endif |
||||
|
||||
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; |
||||
mmc->f_max = chip->sclk / 2; |
||||
mmc->f_min = chip->sclk / 0x100; |
||||
mmc->block_dev.part_type = PART_TYPE_DOS; |
||||
|
||||
mmc_register(mmc); |
||||
|
||||
return 0; |
||||
} |
Loading…
Reference in new issue