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@ -6,7 +6,7 @@ |
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* Licensed under the GPL-2 or later. |
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*/ |
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/* This file shoule be up to date with:
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/* This file should be up to date with:
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* - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List |
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*/ |
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@ -34,12 +34,12 @@ |
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# define ANOMALY_BF533 0 |
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#endif |
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */ |
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/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */ |
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#define ANOMALY_05000074 (1) |
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/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */ |
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#define ANOMALY_05000099 (__SILICON_REVISION__ < 5) |
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/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */ |
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#define ANOMALY_05000105 (1) |
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#define ANOMALY_05000105 (__SILICON_REVISION__ > 2) |
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/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ |
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#define ANOMALY_05000119 (1) |
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
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@ -48,7 +48,7 @@ |
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#define ANOMALY_05000158 (__SILICON_REVISION__ < 5) |
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/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */ |
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#define ANOMALY_05000166 (1) |
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/* Turning Serial Ports on with External Frame Syncs */ |
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/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */ |
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#define ANOMALY_05000167 (1) |
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/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */ |
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#define ANOMALY_05000179 (__SILICON_REVISION__ < 5) |
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@ -67,9 +67,9 @@ |
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/* Current DMA Address Shows Wrong Value During Carry Fix */ |
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#define ANOMALY_05000199 (__SILICON_REVISION__ < 4) |
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/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */ |
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#define ANOMALY_05000200 (__SILICON_REVISION__ < 5) |
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#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4) |
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/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */ |
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#define ANOMALY_05000201 (__SILICON_REVISION__ < 4) |
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#define ANOMALY_05000201 (__SILICON_REVISION__ == 3) |
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/* Possible Infinite Stall with Specific Dual-DAG Situation */ |
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#define ANOMALY_05000202 (__SILICON_REVISION__ < 5) |
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/* Specific Sequence That Can Cause DMA Error or DMA Stopping */ |
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@ -104,7 +104,7 @@ |
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#define ANOMALY_05000242 (__SILICON_REVISION__ < 5) |
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/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */ |
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#define ANOMALY_05000244 (__SILICON_REVISION__ < 5) |
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/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ |
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */ |
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#define ANOMALY_05000245 (1) |
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/* Data CPLBs Should Prevent Spurious Hardware Errors */ |
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#define ANOMALY_05000246 (__SILICON_REVISION__ < 5) |
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@ -137,7 +137,7 @@ |
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/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */ |
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#define ANOMALY_05000270 (__SILICON_REVISION__ < 5) |
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/* Spontaneous Reset of Internal Voltage Regulator */ |
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#define ANOMALY_05000271 (__SILICON_REVISION__ < 4) |
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#define ANOMALY_05000271 (__SILICON_REVISION__ == 3) |
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/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */ |
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#define ANOMALY_05000272 (1) |
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/* Writes to Synchronous SDRAM Memory May Be Lost */ |
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@ -165,14 +165,14 @@ |
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/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */ |
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#define ANOMALY_05000306 (__SILICON_REVISION__ < 5) |
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/* SCKELOW Bit Does Not Maintain State Through Hibernate */ |
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#define ANOMALY_05000307 (1) |
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#define ANOMALY_05000307 (1) /* note: brokenness is noted in documentation, not anomaly sheet */ |
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */ |
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#define ANOMALY_05000310 (1) |
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/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */ |
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#define ANOMALY_05000311 (__SILICON_REVISION__ < 6) |
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/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ |
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#define ANOMALY_05000312 (__SILICON_REVISION__ < 6) |
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/* PPI Is Level-Sensitive on First Transfer */ |
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/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */ |
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#define ANOMALY_05000313 (__SILICON_REVISION__ < 6) |
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/* Killed System MMR Write Completes Erroneously On Next System MMR Access */ |
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#define ANOMALY_05000315 (__SILICON_REVISION__ < 6) |
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@ -205,12 +205,56 @@ |
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* here to show running on older silicon just isn't feasible. |
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*/ |
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/* Internal voltage regulator can't be modified via register writes */ |
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#define ANOMALY_05000066 (__SILICON_REVISION__ < 2) |
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/* Watchpoints (Hardware Breakpoints) are not supported */ |
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#define ANOMALY_05000067 (__SILICON_REVISION__ < 3) |
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/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */ |
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#define ANOMALY_05000070 (__SILICON_REVISION__ < 2) |
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/* Writing FIO_DIR can corrupt a programmable flag's data */ |
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#define ANOMALY_05000079 (__SILICON_REVISION__ < 2) |
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/* Timer Auto-Baud Mode requires the UART clock to be enabled */ |
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#define ANOMALY_05000086 (__SILICON_REVISION__ < 2) |
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/* Internal Clocking Modes on SPORT0 not supported */ |
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#define ANOMALY_05000088 (__SILICON_REVISION__ < 2) |
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/* Internal voltage regulator does not wake up from an RTC wakeup */ |
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#define ANOMALY_05000092 (__SILICON_REVISION__ < 2) |
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/* The IFLUSH instruction must be preceded by a CSYNC instruction */ |
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#define ANOMALY_05000093 (__SILICON_REVISION__ < 2) |
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/* Vectoring to an instruction that is presently being filled into the instruction cache may cause erroneous behavior */ |
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#define ANOMALY_05000095 (__SILICON_REVISION__ < 2) |
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/* PREFETCH, FLUSH, and FLUSHINV must be followed by a CSYNC */ |
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#define ANOMALY_05000096 (__SILICON_REVISION__ < 2) |
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/* Performance Monitor 0 and 1 are swapped when monitoring memory events */ |
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#define ANOMALY_05000097 (__SILICON_REVISION__ < 2) |
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/* 32-bit SPORT DMA will be word reversed */ |
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#define ANOMALY_05000098 (__SILICON_REVISION__ < 2) |
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/* Incorrect status in the UART_IIR register */ |
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#define ANOMALY_05000100 (__SILICON_REVISION__ < 2) |
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/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */ |
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#define ANOMALY_05000101 (__SILICON_REVISION__ < 2) |
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/* Descriptor-based MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */ |
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#define ANOMALY_05000102 (__SILICON_REVISION__ < 2) |
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/* Incorrect value written to the cycle counters */ |
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#define ANOMALY_05000103 (__SILICON_REVISION__ < 2) |
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/* Stores to L1 Data memory incorrect when a specific sequence is followed */ |
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#define ANOMALY_05000104 (__SILICON_REVISION__ < 2) |
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/* Programmable Flag (PF3) functionality not supported in all PPI modes */ |
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#define ANOMALY_05000106 (__SILICON_REVISION__ < 2) |
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/* Data store can be lost when targeting a cache line fill */ |
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#define ANOMALY_05000107 (__SILICON_REVISION__ < 2) |
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/* Reserved bits in SYSCFG register not set at power on */ |
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#define ANOMALY_05000109 (__SILICON_REVISION__ < 3) |
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/* Infinite Core Stall */ |
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#define ANOMALY_05000114 (__SILICON_REVISION__ < 2) |
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/* PPI_FSx may glitch when generated by the on chip Timers */ |
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#define ANOMALY_05000115 (__SILICON_REVISION__ < 2) |
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/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */ |
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#define ANOMALY_05000116 (__SILICON_REVISION__ < 3) |
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/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */ |
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#define ANOMALY_05000117 (__SILICON_REVISION__ < 2) |
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/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */ |
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#define ANOMALY_05000118 (__SILICON_REVISION__ < 2) |
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/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */ |
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#define ANOMALY_05000123 (__SILICON_REVISION__ < 3) |
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/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */ |
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@ -222,7 +266,9 @@ |
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/* DMEM_CONTROL is not set on Reset */ |
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#define ANOMALY_05000137 (__SILICON_REVISION__ < 3) |
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/* SPI boot will not complete if there is a zero fill block in the loader file */ |
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#define ANOMALY_05000138 (__SILICON_REVISION__ < 3) |
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#define ANOMALY_05000138 (__SILICON_REVISION__ == 2) |
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/* Timerx_Config must be set for using the PPI in GP output mode with internal Frame Syncs */ |
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#define ANOMALY_05000139 (__SILICON_REVISION__ < 2) |
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/* Allowing the SPORT RX FIFO to fill will cause an overflow */ |
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#define ANOMALY_05000140 (__SILICON_REVISION__ < 3) |
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/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */ |
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@ -237,17 +283,17 @@ |
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#define ANOMALY_05000145 (__SILICON_REVISION__ < 3) |
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/* MDMA may lose the first few words of a descriptor chain */ |
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#define ANOMALY_05000146 (__SILICON_REVISION__ < 3) |
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/* The source MDMA descriptor may stop with a DMA Error */ |
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/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */ |
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#define ANOMALY_05000147 (__SILICON_REVISION__ < 3) |
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/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */ |
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#define ANOMALY_05000148 (__SILICON_REVISION__ < 3) |
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/* Frame Delay in SPORT Multichannel Mode */ |
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#define ANOMALY_05000153 (__SILICON_REVISION__ < 3) |
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/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */ |
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/* SPORT TFS signal stays active in multichannel mode outside of valid channels */ |
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#define ANOMALY_05000154 (__SILICON_REVISION__ < 3) |
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/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */ |
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#define ANOMALY_05000155 (__SILICON_REVISION__ < 3) |
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/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */ |
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/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */ |
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#define ANOMALY_05000157 (__SILICON_REVISION__ < 3) |
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/* SPORT transmit data is not gated by external frame sync in certain conditions */ |
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#define ANOMALY_05000163 (__SILICON_REVISION__ < 3) |
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@ -275,12 +321,15 @@ |
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#define ANOMALY_05000206 (__SILICON_REVISION__ < 3) |
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/* Anomalies that don't exist on this proc */ |
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#define ANOMALY_05000171 (0) |
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#define ANOMALY_05000266 (0) |
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#define ANOMALY_05000323 (0) |
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#define ANOMALY_05000353 (1) |
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#define ANOMALY_05000362 (1) |
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#define ANOMALY_05000380 (0) |
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#define ANOMALY_05000386 (1) |
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#define ANOMALY_05000412 (0) |
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#define ANOMALY_05000430 (0) |
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#define ANOMALY_05000432 (0) |
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#define ANOMALY_05000435 (0) |
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#define ANOMALY_05000447 (0) |
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