@ -23,6 +23,7 @@
*/
# include <common.h>
# include <asm/io.h>
# include <asm/arch/at91sam9261.h>
# include <asm/arch/at91sam9261_matrix.h>
# include <asm/arch/at91sam9_smc.h>
@ -31,7 +32,6 @@
# include <asm/arch/at91_rstc.h>
# include <asm/arch/clk.h>
# include <asm/arch/gpio.h>
# include <asm/arch/io.h>
# include <lcd.h>
# include <atmel_lcdc.h>
# if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
@ -49,44 +49,48 @@ DECLARE_GLOBAL_DATA_PTR;
# ifdef CONFIG_CMD_NAND
static void at91sam9261ek_nand_hw_init ( void )
{
struct at91_smc * smc = ( struct at91_smc * ) ATMEL_BASE_SMC ;
struct at91_matrix * matrix = ( struct at91_matrix * ) ATMEL_BASE_MATRIX ;
struct at91_pmc * pmc = ( struct at91_pmc * ) ATMEL_BASE_PMC ;
unsigned long csa ;
/* Enable CS3 */
csa = at91_sys_read ( AT91_MATRIX_EBICSA ) ;
at91_sys_write ( AT91_MATRIX_EBICSA ,
csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA ) ;
csa = readl ( & matrix - > ebicsa ) ;
csa | = AT91_MATRIX_CS3A_SMC_SMARTMEDIA ;
writel ( csa , & matrix - > ebicsa ) ;
/* Configure SMC CS3 for NAND/SmartMedia */
# ifdef CONFIG_AT91SAM9G10EK
at91_sys_ write( AT91_SMC_SETUP ( 3 ) ,
AT91_SMC_NWE SETUP_ ( 2 ) | AT91_SMC_NCS_WR SETUP_ ( 0 ) |
AT91_SMC_NRDSETUP_ ( 2 ) | AT91_SMC_NCS_RDSETUP_ ( 0 ) ) ;
at91_sys_ write( AT91_SMC_PULSE ( 3 ) ,
AT91_SMC_NWE PULSE_ ( 3 ) | AT91_SMC_NCS_WR PULSE_ ( 7 ) |
AT91_SMC_NRDPULSE_ ( 3 ) | AT91_SMC_NCS_RDPULSE_ ( 7 ) ) ;
at91_sys_write ( AT91_SMC_CYCLE ( 3 ) ,
AT91_SMC_NWECYCLE_ ( 7 ) | AT91_SMC_NRDCYCLE_ ( 7 ) ) ;
writel ( AT91_SMC_SETUP_NWE ( 2 ) | AT91_SMC_SETUP_NCS_WR ( 0 ) |
AT91_SMC_SETUP_NRD ( 2 ) | AT91_SMC_SETUP_NCS_RD ( 0 ) ,
& smc - > cs [ 3 ] . setup ) ;
writel ( AT91_SMC_PULSE_NWE ( 3 ) | AT91_SMC_PULSE_NCS_WR ( 7 ) |
AT91_SMC_PULSE_NRD ( 3 ) | AT91_SMC_PULSE_NCS_RD ( 7 ) ,
& smc - > cs [ 3 ] . pulse ) ;
writel ( AT91_SMC_CYCLE_NWE ( 7 ) | AT91_SMC_CYCLE_NRD ( 7 ) ,
& smc - > cs [ 3 ] . cycle ) ;
# else
at91_sys_ write( AT91_SMC_SETUP ( 3 ) ,
AT91_SMC_NWE SETUP_ ( 1 ) | AT91_SMC_NCS_WR SETUP_ ( 0 ) |
AT91_SMC_NRDSETUP_ ( 1 ) | AT91_SMC_NCS_RDSETUP_ ( 0 ) ) ;
at91_sys_ write( AT91_SMC_PULSE ( 3 ) ,
AT91_SMC_NWE PULSE_ ( 3 ) | AT91_SMC_NCS_WR PULSE_ ( 3 ) |
AT91_SMC_NRDPULSE_ ( 3 ) | AT91_SMC_NCS_RDPULSE_ ( 3 ) ) ;
at91_sys_write ( AT91_SMC_CYCLE ( 3 ) ,
AT91_SMC_NWECYCLE_ ( 5 ) | AT91_SMC_NRDCYCLE_ ( 5 ) ) ;
writel ( AT91_SMC_SETUP_NWE ( 1 ) | AT91_SMC_SETUP_NCS_WR ( 0 ) |
AT91_SMC_SETUP_NRD ( 1 ) | AT91_SMC_SETUP_NCS_RD ( 0 ) ,
& smc - > cs [ 3 ] . setup ) ;
writel ( AT91_SMC_PULSE_NWE ( 3 ) | AT91_SMC_PULSE_NCS_WR ( 3 ) |
AT91_SMC_PULSE_NRD ( 3 ) | AT91_SMC_PULSE_NCS_RD ( 3 ) ,
& smc - > cs [ 3 ] . pulse ) ;
writel ( AT91_SMC_CYCLE_NWE ( 5 ) | AT91_SMC_CYCLE_NRD ( 5 ) ,
& smc - > cs [ 3 ] . cycle ) ;
# endif
at91_sys_write ( AT91_SMC_MODE ( 3 ) ,
AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
AT91_SMC_EXNWMODE_DISABLE |
writel ( AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABLE |
# ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_DBW_16 |
AT91_SMC_MODE_ DBW_16 |
# else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_DBW_8 |
AT91_SMC_MODE_ DBW_8 |
# endif
AT91_SMC_TDF_ ( 2 ) ) ;
AT91_SMC_MODE_TDF_CYCLE ( 2 ) ,
& smc - > cs [ 3 ] . mode ) ;
at91_sys_write ( AT91_PMC_PCER , 1 < < AT91SAM9261_ID_PIOC ) ;
writel ( 1 < < ATMEL_ID_PIOC , & pmc - > pcer ) ;
/* Configure RDY/BSY */
at91_set_gpio_input ( CONFIG_SYS_NAND_READY_PIN , 1 ) ;
@ -102,35 +106,37 @@ static void at91sam9261ek_nand_hw_init(void)
# ifdef CONFIG_DRIVER_DM9000
static void at91sam9261ek_dm9000_hw_init ( void )
{
struct at91_smc * smc = ( struct at91_smc * ) ATMEL_BASE_SMC ;
/* Configure SMC CS2 for DM9000 */
# ifdef CONFIG_AT91SAM9G10EK
at91_sys_ write( AT91_SMC_SETUP ( 2 ) ,
AT91_SMC_NWE SETUP_ ( 3 ) | AT91_SMC_NCS_WR SETUP_ ( 0 ) |
AT91_SMC_NRDSETUP_ ( 3 ) | AT91_SMC_NCS_RDSETUP_ ( 0 ) ) ;
at91_sys_ write( AT91_SMC_PULSE ( 2 ) ,
AT91_SMC_NWE PULSE_ ( 6 ) | AT91_SMC_NCS_WR PULSE_ ( 8 ) |
AT91_SMC_NRDPULSE_ ( 6 ) | AT91_SMC_NCS_RDPULSE_ ( 8 ) ) ;
at91_sys_write ( AT91_SMC_CYCLE ( 2 ) ,
AT91_SMC_NWECYCLE_ ( 20 ) | AT91_SMC_NRDCYCLE_ ( 20 ) ) ;
at91_sys_ write( AT91_SMC_MODE ( 2 ) ,
AT91_SMC_READMODE | AT91_SMC_WRITEMOD E |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
AT91_SMC_TDF_ ( 1 ) ) ;
writel ( AT91_SMC_SETUP_NWE ( 3 ) | AT91_SMC_SETUP_NCS_WR ( 0 ) |
AT91_SMC_SETUP_NRD ( 3 ) | AT91_SMC_SETUP_NCS_RD ( 0 ) ,
& smc - > cs [ 2 ] . setup ) ;
writel ( AT91_SMC_PULSE_NWE ( 6 ) | AT91_SMC_PULSE_NCS_WR ( 8 ) |
AT91_SMC_PULSE_NRD ( 6 ) | AT91_SMC_PULSE_NCS_RD ( 8 ) ,
& smc - > cs [ 2 ] . pulse ) ;
writel ( AT91_SMC_CYCLE_NWE ( 20 ) | AT91_SMC_CYCLE_NRD ( 20 ) ,
& smc - > cs [ 2 ] . cycle ) ;
writel ( AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABL E |
AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
AT91_SMC_MODE_TDF_CYCLE ( 1 ) ,
& smc - > cs [ 2 ] . mode ) ;
# else
at91_sys_ write( AT91_SMC_SETUP ( 2 ) ,
AT91_SMC_NWE SETUP_ ( 2 ) | AT91_SMC_NCS_WR SETUP_ ( 0 ) |
AT91_SMC_NRDSETUP_ ( 2 ) | AT91_SMC_NCS_RDSETUP_ ( 0 ) ) ;
at91_sys_ write( AT91_SMC_PULSE ( 2 ) ,
AT91_SMC_NWE PULSE_ ( 4 ) | AT91_SMC_NCS_WR PULSE_ ( 8 ) |
AT91_SMC_NRDPULSE_ ( 4 ) | AT91_SMC_NCS_RDPULSE_ ( 8 ) ) ;
at91_sys_write ( AT91_SMC_CYCLE ( 2 ) ,
AT91_SMC_NWECYCLE_ ( 16 ) | AT91_SMC_NRDCYCLE_ ( 16 ) ) ;
at91_sys_ write( AT91_SMC_MODE ( 2 ) ,
AT91_SMC_READMODE | AT91_SMC_WRITEMOD E |
AT91_SMC_EXNWMODE_DISABLE |
AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
AT91_SMC_TDF_ ( 1 ) ) ;
writel ( AT91_SMC_SETUP_NWE ( 3 ) | AT91_SMC_SETUP_NCS_WR ( 0 ) |
AT91_SMC_SETUP_NRD ( 2 ) | AT91_SMC_SETUP_NCS_RD ( 0 ) ,
& smc - > cs [ 2 ] . setup ) ;
writel ( AT91_SMC_PULSE_NWE ( 4 ) | AT91_SMC_PULSE_NCS_WR ( 8 ) |
AT91_SMC_PULSE_NRD ( 4 ) | AT91_SMC_PULSE_NCS_RD ( 8 ) ,
& smc - > cs [ 2 ] . pulse ) ;
writel ( AT91_SMC_CYCLE_NWE ( 16 ) | AT91_SMC_CYCLE_NRD ( 16 ) ,
& smc - > cs [ 2 ] . cycle ) ;
writel ( AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
AT91_SMC_MODE_EXNW_DISABL E |
AT91_SMC_MODE_BAT | AT91_SMC_MODE_DBW_16 |
AT91_SMC_MODE_TDF_CYCLE ( 1 ) ,
& smc - > cs [ 2 ] . mode ) ;
# endif
/* Configure Reset signal as output */
@ -156,7 +162,7 @@ vidinfo_t panel_info = {
vl_vsync_len : 1 ,
vl_upper_margin : 1 ,
vl_lower_margin : 0 ,
mmio : AT91SAM9261_LCDC_BASE ,
mmio : ATMEL_BASE_LCDC ,
} ;
void lcd_enable ( void )
@ -171,6 +177,8 @@ void lcd_disable(void)
static void at91sam9261ek_lcd_hw_init ( void )
{
struct at91_pmc * pmc = ( struct at91_pmc * ) ATMEL_BASE_PMC ;
at91_set_A_periph ( AT91_PIN_PB1 , 0 ) ; /* LCDHSYNC */
at91_set_A_periph ( AT91_PIN_PB2 , 0 ) ; /* LCDDOTCK */
at91_set_A_periph ( AT91_PIN_PB3 , 0 ) ; /* LCDDEN */
@ -194,12 +202,11 @@ static void at91sam9261ek_lcd_hw_init(void)
at91_set_B_periph ( AT91_PIN_PB27 , 0 ) ; /* LCDD22 */
at91_set_B_periph ( AT91_PIN_PB28 , 0 ) ; /* LCDD23 */
at91_sys_ write( AT91_PMC_SCER , AT91_PMC_HCK1 ) ;
writel ( AT91_PMC_HCK1 , & pmc - > scer ) ;
# ifdef CONFIG_AT91SAM9G10EK
gd - > fb_base = CONFIG_AT91SAM9G10_LCD_BASE ;
# else
gd - > fb_base = AT91SAM9261_SRAM_BASE ;
/* For 9G10EK, let U-Boot allocate the framebuffer in SDRAM */
# ifdef CONFIG_AT91SAM9261EK
gd - > fb_base = ATMEL_BASE_SRAM ;
# endif
}
@ -217,7 +224,7 @@ void lcd_show_board_info(void)
lcd_printf ( " (C) 2008 ATMEL Corp \n " ) ;
lcd_printf ( " at91support@atmel.com \n " ) ;
lcd_printf ( " %s CPU at %s MHz \n " ,
CONFIG_SYS_AT91 _CPU_NAME,
ATMEL _CPU_NAME,
strmhz ( temp , get_cpu_clk_rate ( ) ) ) ;
dram_size = 0 ;
@ -246,9 +253,9 @@ int board_init(void)
gd - > bd - > bi_arch_number = MACH_TYPE_AT91SAM9261EK ;
# endif
/* adress of boot parameters */
gd - > bd - > bi_boot_params = PHYS_SDRAM + 0x100 ;
gd - > bd - > bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100 ;
at91_serial_hw_init ( ) ;
at91_seriald _hw_init ( ) ;
# ifdef CONFIG_CMD_NAND
at91sam9261ek_nand_hw_init ( ) ;
# endif
@ -273,8 +280,9 @@ int board_eth_init(bd_t *bis)
int dram_init ( void )
{
gd - > bd - > bi_dram [ 0 ] . start = PHYS_SDRAM ;
gd - > bd - > bi_dram [ 0 ] . size = PHYS_SDRAM_SIZE ;
gd - > ram_size = get_ram_size ( ( void * ) CONFIG_SYS_SDRAM_BASE ,
CONFIG_SYS_SDRAM_SIZE ) ;
return 0 ;
}