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@ -15,15 +15,13 @@ |
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#include <linux/bch.h> |
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#include <linux/compiler.h> |
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#include <nand.h> |
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#ifdef CONFIG_AM33XX |
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#include <asm/arch/elm.h> |
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#endif |
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#include <asm/omap_elm.h> |
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#define BADBLOCK_MARKER_LENGTH 2 |
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#define SECTOR_BYTES 512 |
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static uint8_t cs; |
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static __maybe_unused struct nand_ecclayout hw_nand_oob = |
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GPMC_NAND_HW_ECC_LAYOUT; |
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static __maybe_unused struct nand_ecclayout hw_bch8_nand_oob = |
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GPMC_NAND_HW_BCH8_ECC_LAYOUT; |
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static __maybe_unused struct nand_ecclayout omap_ecclayout; |
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/*
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* omap_nand_hwcontrol - Set the address pointers corretly for the |
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@ -233,6 +231,7 @@ struct nand_bch_priv { |
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uint8_t type; |
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uint8_t nibbles; |
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struct bch_control *control; |
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enum omap_ecc ecc_scheme; |
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}; |
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/* bch types */ |
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@ -274,17 +273,15 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) |
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{ |
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uint32_t val; |
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uint32_t dev_width = (chip->options & NAND_BUSWIDTH_16) >> 1; |
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#ifdef CONFIG_AM33XX |
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uint32_t unused_length = 0; |
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#endif |
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uint32_t wr_mode = BCH_WRAPMODE_6; |
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struct nand_bch_priv *bch = chip->priv; |
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/* Clear the ecc result registers, select ecc reg as 1 */ |
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writel(ECCCLEAR | ECCRESULTREG1, &gpmc_cfg->ecc_control); |
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#ifdef CONFIG_AM33XX |
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wr_mode = BCH_WRAPMODE_1; |
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if (bch->ecc_scheme == OMAP_ECC_BCH8_CODE_HW) { |
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wr_mode = BCH_WRAPMODE_1; |
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switch (bch->nibbles) { |
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case ECC_BCH4_NIBBLES: |
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@ -320,7 +317,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) |
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val |= (unused_length << 22); |
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break; |
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} |
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#else |
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} else { |
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/*
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* This ecc_size_config setting is for BCH sw library. |
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* |
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@ -333,7 +330,7 @@ static void omap_hwecc_init_bch(struct nand_chip *chip, int32_t mode) |
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* size1 = 32 (skip 32 nibbles = 16 bytes per sector in spare area) |
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*/ |
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val = (32 << 22) | (0 << 12); |
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#endif |
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} |
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/* ecc size configuration */ |
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writel(val, &gpmc_cfg->ecc_size_config); |
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@ -376,9 +373,9 @@ static void __maybe_unused omap_ecc_disable(struct mtd_info *mtd) |
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} |
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/*
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* BCH8 support (needs ELM and thus AM33xx-only) |
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* BCH support using ELM module |
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*/ |
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#ifdef CONFIG_AM33XX |
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#ifdef CONFIG_NAND_OMAP_ELM |
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/*
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* omap_read_bch8_result - Read BCH result for BCH8 level |
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* |
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@ -631,20 +628,20 @@ static int omap_read_page_bch(struct mtd_info *mtd, struct nand_chip *chip, |
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} |
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return 0; |
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} |
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#endif /* CONFIG_AM33XX */ |
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#endif /* CONFIG_NAND_OMAP_ELM */ |
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/*
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* OMAP3 BCH8 support (with BCH library) |
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*/ |
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#ifdef CONFIG_NAND_OMAP_BCH8 |
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#ifdef CONFIG_BCH |
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/*
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* omap_calculate_ecc_bch - Read BCH ECC result |
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* omap_calculate_ecc_bch_sw - Read BCH ECC result |
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* |
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* @mtd: MTD device structure |
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* @dat: The pointer to data on which ecc is computed (unused here) |
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* @ecc: The ECC output buffer |
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*/ |
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static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, |
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static int omap_calculate_ecc_bch_sw(struct mtd_info *mtd, const uint8_t *dat, |
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uint8_t *ecc) |
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{ |
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int ret = 0; |
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@ -689,13 +686,13 @@ static int omap_calculate_ecc_bch(struct mtd_info *mtd, const uint8_t *dat, |
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} |
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/**
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* omap_correct_data_bch - Decode received data and correct errors |
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* omap_correct_data_bch_sw - Decode received data and correct errors |
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* @mtd: MTD device structure |
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* @data: page data |
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* @read_ecc: ecc read from nand flash |
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* @calc_ecc: ecc read from HW ECC registers |
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*/ |
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static int omap_correct_data_bch(struct mtd_info *mtd, u_char *data, |
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static int omap_correct_data_bch_sw(struct mtd_info *mtd, u_char *data, |
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u_char *read_ecc, u_char *calc_ecc) |
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{ |
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int i, count; |
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@ -752,7 +749,150 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) |
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chip_priv->control = NULL; |
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} |
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} |
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#endif /* CONFIG_NAND_OMAP_BCH8 */ |
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#endif /* CONFIG_BCH */ |
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/**
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* omap_select_ecc_scheme - configures driver for particular ecc-scheme |
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* @nand: NAND chip device structure |
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* @ecc_scheme: ecc scheme to configure |
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* @pagesize: number of main-area bytes per page of NAND device |
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* @oobsize: number of OOB/spare bytes per page of NAND device |
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*/ |
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static int omap_select_ecc_scheme(struct nand_chip *nand, |
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enum omap_ecc ecc_scheme, unsigned int pagesize, unsigned int oobsize) { |
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struct nand_bch_priv *bch = nand->priv; |
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struct nand_ecclayout *ecclayout = nand->ecc.layout; |
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int eccsteps = pagesize / SECTOR_BYTES; |
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int i; |
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switch (ecc_scheme) { |
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case OMAP_ECC_HAM1_CODE_SW: |
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debug("nand: selected OMAP_ECC_HAM1_CODE_SW\n"); |
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/* For this ecc-scheme, ecc.bytes, ecc.layout, ... are
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* initialized in nand_scan_tail(), so just set ecc.mode */ |
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bch_priv.control = NULL; |
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bch_priv.type = 0; |
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nand->ecc.mode = NAND_ECC_SOFT; |
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nand->ecc.layout = NULL; |
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nand->ecc.size = pagesize; |
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bch->ecc_scheme = OMAP_ECC_HAM1_CODE_SW; |
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break; |
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case OMAP_ECC_HAM1_CODE_HW: |
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debug("nand: selected OMAP_ECC_HAM1_CODE_HW\n"); |
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/* check ecc-scheme requirements before updating ecc info */ |
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if ((3 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { |
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printf("nand: error: insufficient OOB: require=%d\n", ( |
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(3 * eccsteps) + BADBLOCK_MARKER_LENGTH)); |
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return -EINVAL; |
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} |
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bch_priv.control = NULL; |
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bch_priv.type = 0; |
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/* populate ecc specific fields */ |
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nand->ecc.mode = NAND_ECC_HW; |
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nand->ecc.strength = 1; |
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nand->ecc.size = SECTOR_BYTES; |
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nand->ecc.bytes = 3; |
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nand->ecc.hwctl = omap_enable_hwecc; |
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nand->ecc.correct = omap_correct_data; |
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nand->ecc.calculate = omap_calculate_ecc; |
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/* define ecc-layout */ |
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ecclayout->eccbytes = nand->ecc.bytes * eccsteps; |
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for (i = 0; i < ecclayout->eccbytes; i++) |
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ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; |
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ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; |
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ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - |
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BADBLOCK_MARKER_LENGTH; |
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bch->ecc_scheme = OMAP_ECC_HAM1_CODE_HW; |
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break; |
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case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: |
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#ifdef CONFIG_BCH |
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debug("nand: selected OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); |
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/* check ecc-scheme requirements before updating ecc info */ |
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if ((13 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { |
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printf("nand: error: insufficient OOB: require=%d\n", ( |
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(13 * eccsteps) + BADBLOCK_MARKER_LENGTH)); |
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return -EINVAL; |
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} |
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/* check if BCH S/W library can be used for error detection */ |
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bch_priv.control = init_bch(13, 8, 0x201b); |
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if (!bch_priv.control) { |
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printf("nand: error: could not init_bch()\n"); |
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return -ENODEV; |
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} |
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bch_priv.type = ECC_BCH8; |
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/* populate ecc specific fields */ |
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nand->ecc.mode = NAND_ECC_HW; |
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nand->ecc.strength = 8; |
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nand->ecc.size = SECTOR_BYTES; |
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nand->ecc.bytes = 13; |
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nand->ecc.hwctl = omap_enable_ecc_bch; |
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nand->ecc.correct = omap_correct_data_bch_sw; |
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nand->ecc.calculate = omap_calculate_ecc_bch_sw; |
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/* define ecc-layout */ |
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ecclayout->eccbytes = nand->ecc.bytes * eccsteps; |
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ecclayout->eccpos[0] = BADBLOCK_MARKER_LENGTH; |
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for (i = 1; i < ecclayout->eccbytes; i++) { |
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if (i % nand->ecc.bytes) |
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ecclayout->eccpos[i] = |
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ecclayout->eccpos[i - 1] + 1; |
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else |
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ecclayout->eccpos[i] = |
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ecclayout->eccpos[i - 1] + 2; |
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} |
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ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; |
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ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - |
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BADBLOCK_MARKER_LENGTH; |
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omap_hwecc_init_bch(nand, NAND_ECC_READ); |
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bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW; |
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break; |
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#else |
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printf("nand: error: CONFIG_BCH required for ECC\n"); |
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return -EINVAL; |
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#endif |
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case OMAP_ECC_BCH8_CODE_HW: |
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#ifdef CONFIG_NAND_OMAP_ELM |
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debug("nand: selected OMAP_ECC_BCH8_CODE_HW\n"); |
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/* check ecc-scheme requirements before updating ecc info */ |
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if ((14 * eccsteps) + BADBLOCK_MARKER_LENGTH > oobsize) { |
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printf("nand: error: insufficient OOB: require=%d\n", ( |
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(14 * eccsteps) + BADBLOCK_MARKER_LENGTH)); |
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return -EINVAL; |
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} |
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/* intialize ELM for ECC error detection */ |
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elm_init(); |
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bch_priv.type = ECC_BCH8; |
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/* populate ecc specific fields */ |
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nand->ecc.mode = NAND_ECC_HW; |
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nand->ecc.strength = 8; |
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nand->ecc.size = SECTOR_BYTES; |
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nand->ecc.bytes = 14; |
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nand->ecc.hwctl = omap_enable_ecc_bch; |
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nand->ecc.correct = omap_correct_data_bch; |
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nand->ecc.calculate = omap_calculate_ecc_bch; |
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nand->ecc.read_page = omap_read_page_bch; |
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/* define ecc-layout */ |
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ecclayout->eccbytes = nand->ecc.bytes * eccsteps; |
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for (i = 0; i < ecclayout->eccbytes; i++) |
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ecclayout->eccpos[i] = i + BADBLOCK_MARKER_LENGTH; |
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ecclayout->oobfree[0].offset = i + BADBLOCK_MARKER_LENGTH; |
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ecclayout->oobfree[0].length = oobsize - ecclayout->eccbytes - |
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BADBLOCK_MARKER_LENGTH; |
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bch->ecc_scheme = OMAP_ECC_BCH8_CODE_HW; |
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break; |
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#else |
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printf("nand: error: CONFIG_NAND_OMAP_ELM required for ECC\n"); |
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return -EINVAL; |
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#endif |
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default: |
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debug("nand: error: ecc scheme not enabled or supported\n"); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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#ifndef CONFIG_SPL_BUILD |
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/*
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@ -763,77 +903,45 @@ static void __maybe_unused omap_free_bch(struct mtd_info *mtd) |
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* @eccstrength - the number of bits that could be corrected |
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* (1 - hamming, 4 - BCH4, 8 - BCH8, 16 - BCH16) |
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*/ |
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void omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) |
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int __maybe_unused omap_nand_switch_ecc(uint32_t hardware, uint32_t eccstrength) |
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{ |
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struct nand_chip *nand; |
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struct mtd_info *mtd; |
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int err = 0; |
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if (nand_curr_device < 0 || |
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nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE || |
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!nand_info[nand_curr_device].name) { |
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printf("Error: Can't switch ecc, no devices available\n"); |
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return; |
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printf("nand: error: no NAND devices found\n"); |
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return -ENODEV; |
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} |
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mtd = &nand_info[nand_curr_device]; |
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nand = mtd->priv; |
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nand->options |= NAND_OWN_BUFFERS; |
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/* Reset ecc interface */ |
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nand->ecc.mode = NAND_ECC_NONE; |
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nand->ecc.read_page = NULL; |
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nand->ecc.write_page = NULL; |
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nand->ecc.read_oob = NULL; |
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nand->ecc.write_oob = NULL; |
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nand->ecc.hwctl = NULL; |
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nand->ecc.correct = NULL; |
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nand->ecc.calculate = NULL; |
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nand->ecc.strength = eccstrength; |
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/* Setup the ecc configurations again */ |
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if (hardware) { |
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if (eccstrength == 1) { |
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nand->ecc.mode = NAND_ECC_HW; |
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nand->ecc.layout = &hw_nand_oob; |
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nand->ecc.size = 512; |
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nand->ecc.bytes = 3; |
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nand->ecc.hwctl = omap_enable_hwecc; |
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nand->ecc.correct = omap_correct_data; |
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nand->ecc.calculate = omap_calculate_ecc; |
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omap_hwecc_init(nand); |
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printf("1-bit hamming HW ECC selected\n"); |
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} |
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#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) |
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else if (eccstrength == 8) { |
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nand->ecc.mode = NAND_ECC_HW; |
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nand->ecc.layout = &hw_bch8_nand_oob; |
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nand->ecc.size = 512; |
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#ifdef CONFIG_AM33XX |
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nand->ecc.bytes = 14; |
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nand->ecc.read_page = omap_read_page_bch; |
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#else |
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nand->ecc.bytes = 13; |
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#endif |
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nand->ecc.hwctl = omap_enable_ecc_bch; |
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nand->ecc.correct = omap_correct_data_bch; |
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nand->ecc.calculate = omap_calculate_ecc_bch; |
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omap_hwecc_init_bch(nand, NAND_ECC_READ); |
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printf("8-bit BCH HW ECC selected\n"); |
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err = omap_select_ecc_scheme(nand, |
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OMAP_ECC_HAM1_CODE_HW, |
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mtd->writesize, mtd->oobsize); |
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} else if (eccstrength == 8) { |
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err = omap_select_ecc_scheme(nand, |
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OMAP_ECC_BCH8_CODE_HW, |
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mtd->writesize, mtd->oobsize); |
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} else { |
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printf("nand: error: unsupported ECC scheme\n"); |
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return -EINVAL; |
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} |
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#endif |
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} else { |
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nand->ecc.mode = NAND_ECC_SOFT; |
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/* Use mtd default settings */ |
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nand->ecc.layout = NULL; |
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nand->ecc.size = 0; |
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printf("SW ECC selected\n"); |
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err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, |
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mtd->writesize, mtd->oobsize); |
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} |
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/* Update NAND handling after ECC mode switch */ |
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nand_scan_tail(mtd); |
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nand->options &= ~NAND_OWN_BUFFERS; |
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if (!err) |
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err = nand_scan_tail(mtd); |
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return err; |
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} |
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#endif /* CONFIG_SPL_BUILD */ |
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@ -856,7 +964,7 @@ int board_nand_init(struct nand_chip *nand) |
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{ |
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int32_t gpmc_config = 0; |
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cs = 0; |
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int err = 0; |
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/*
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* xloader/Uboot's gpmc configuration would have configured GPMC for |
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* nand type of memory. The following logic scans and latches on to the |
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@ -873,7 +981,7 @@ int board_nand_init(struct nand_chip *nand) |
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cs++; |
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} |
|
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|
|
if (cs >= GPMC_MAX_CS) { |
|
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|
|
printf("NAND: Unable to find NAND settings in " |
|
|
|
|
printf("nand: error: Unable to find NAND settings in " |
|
|
|
|
"GPMC Configuration - quitting\n"); |
|
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|
|
return -ENODEV; |
|
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|
} |
|
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|
@ -885,64 +993,27 @@ int board_nand_init(struct nand_chip *nand) |
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nand->IO_ADDR_R = (void __iomem *)&gpmc_cfg->cs[cs].nand_dat; |
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|
nand->IO_ADDR_W = (void __iomem *)&gpmc_cfg->cs[cs].nand_cmd; |
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|
nand->cmd_ctrl = omap_nand_hwcontrol; |
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|
|
nand->options = NAND_NO_PADDING | NAND_CACHEPRG; |
|
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|
|
nand->priv = &bch_priv; |
|
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|
|
nand->cmd_ctrl = omap_nand_hwcontrol; |
|
|
|
|
nand->options |= NAND_NO_PADDING | NAND_CACHEPRG; |
|
|
|
|
/* If we are 16 bit dev, our gpmc config tells us that */ |
|
|
|
|
if ((readl(&gpmc_cfg->cs[cs].config1) & 0x3000) == 0x1000) |
|
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|
nand->options |= NAND_BUSWIDTH_16; |
|
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|
|
nand->chip_delay = 100; |
|
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|
|
nand->ecc.layout = &omap_ecclayout; |
|
|
|
|
|
|
|
|
|
#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) |
|
|
|
|
#ifdef CONFIG_AM33XX |
|
|
|
|
/* AM33xx uses the ELM */ |
|
|
|
|
/* required in case of BCH */ |
|
|
|
|
elm_init(); |
|
|
|
|
#else |
|
|
|
|
/*
|
|
|
|
|
* Whereas other OMAP based SoC do not have the ELM, they use the BCH |
|
|
|
|
* SW library. |
|
|
|
|
*/ |
|
|
|
|
bch_priv.control = init_bch(13, 8, 0x201b /* hw polynominal */); |
|
|
|
|
if (!bch_priv.control) { |
|
|
|
|
puts("Could not init_bch()\n"); |
|
|
|
|
return -ENODEV; |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
/* BCH info that will be correct for SPL or overridden otherwise. */ |
|
|
|
|
nand->priv = &bch_priv; |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
/* Default ECC mode */ |
|
|
|
|
#if defined(CONFIG_AM33XX) || defined(CONFIG_NAND_OMAP_BCH8) |
|
|
|
|
nand->ecc.mode = NAND_ECC_HW; |
|
|
|
|
nand->ecc.layout = &hw_bch8_nand_oob; |
|
|
|
|
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; |
|
|
|
|
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; |
|
|
|
|
nand->ecc.strength = 8; |
|
|
|
|
nand->ecc.hwctl = omap_enable_ecc_bch; |
|
|
|
|
nand->ecc.correct = omap_correct_data_bch; |
|
|
|
|
nand->ecc.calculate = omap_calculate_ecc_bch; |
|
|
|
|
#ifdef CONFIG_AM33XX |
|
|
|
|
nand->ecc.read_page = omap_read_page_bch; |
|
|
|
|
#endif |
|
|
|
|
omap_hwecc_init_bch(nand, NAND_ECC_READ); |
|
|
|
|
#else |
|
|
|
|
#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_NAND_SOFTECC) |
|
|
|
|
nand->ecc.mode = NAND_ECC_SOFT; |
|
|
|
|
/* select ECC scheme */ |
|
|
|
|
#if defined(CONFIG_NAND_OMAP_ECCSCHEME) |
|
|
|
|
err = omap_select_ecc_scheme(nand, CONFIG_NAND_OMAP_ECCSCHEME, |
|
|
|
|
CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE); |
|
|
|
|
#else |
|
|
|
|
nand->ecc.mode = NAND_ECC_HW; |
|
|
|
|
nand->ecc.layout = &hw_nand_oob; |
|
|
|
|
nand->ecc.size = CONFIG_SYS_NAND_ECCSIZE; |
|
|
|
|
nand->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES; |
|
|
|
|
nand->ecc.hwctl = omap_enable_hwecc; |
|
|
|
|
nand->ecc.correct = omap_correct_data; |
|
|
|
|
nand->ecc.calculate = omap_calculate_ecc; |
|
|
|
|
nand->ecc.strength = 1; |
|
|
|
|
omap_hwecc_init(nand); |
|
|
|
|
#endif |
|
|
|
|
/* pagesize and oobsize are not required to configure sw ecc-scheme */ |
|
|
|
|
err = omap_select_ecc_scheme(nand, OMAP_ECC_HAM1_CODE_SW, |
|
|
|
|
0, 0); |
|
|
|
|
#endif |
|
|
|
|
if (err) |
|
|
|
|
return err; |
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_SPL_BUILD |
|
|
|
|
if (nand->options & NAND_BUSWIDTH_16) |
|
|
|
|
|
Tom Rini
11 years ago