powerpc/mpc85xx: SECURE BOOT- Add secure boot target for B4860QDS

Changes:
1. L2 cache is being invalidated by Boot ROM code for e6500 core.
   So removing the invalidation from start.S
2. Clear the LAW and corresponding configuration for CPC. Boot ROM
   code uses it as hosekeeping area.
3. For Secure boot, CPC is configured as SRAM and used as house
   keeping area. This configuration is to be disabled once in uboot.
   Earlier this disabling of CPC as SRAM was happening in cpu_init_r.
   As a result cache invalidation function was getting skipped in
   case CPC is configured as SRAM.This was causing random crashes.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

README

@@ -427,6 +427,10 @@ The following options need to be configured:
 		In this mode, a single differential clock is used to supply
 		clocks to the sysclock, ddrclock and usbclock.
 
+		CONFIG_SYS_CPC_REINIT_F
+		This CONFIG is defined when the CPC is configured as SRAM at the
+		time of U-boot entry and is required to be re-initialized.
+
 - Generic CPU options:
 		CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN
 

arch/powerpc/cpu/mpc85xx/cpu_init.c

@@ -173,17 +173,14 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 #endif
 
 #ifdef CONFIG_SYS_FSL_CPC
-static void enable_cpc(void)
+#if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
+static void disable_cpc_sram(void)
 {
 	int i;
-	u32 size = 0;
 
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
-		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
-		size += CPC_CFG0_SZ_K(cpccfg0);
-#ifdef CONFIG_RAMBOOT_PBL
 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 			/* find and disable LAW of SRAM */
 			struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
@@ -198,8 +195,21 @@ static void enable_cpc(void)
 			out_be32(&cpc->cpccsr0, 0);
 			out_be32(&cpc->cpcsrcr0, 0);
 		}
+	}
+}
 #endif
 
+static void enable_cpc(void)
+{
+	int i;
+	u32 size = 0;
+
+	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+
+	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+		u32 cpccfg0 = in_be32(&cpc->cpccfg0);
+		size += CPC_CFG0_SZ_K(cpccfg0);
+
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 #endif
@@ -298,6 +308,10 @@ void cpu_init_f (void)
 	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 	if (law.index != -1)
 		disable_law(law.index);
+
+#if defined(CONFIG_SYS_CPC_REINIT_F)
+	disable_cpc_sram();
+#endif
 #endif
 
 #ifdef CONFIG_CPM2
@@ -598,6 +612,9 @@ skip_l2:
 	puts("disabled\n");
 #endif
 
+#if defined(CONFIG_RAMBOOT_PBL)
+	disable_cpc_sram();
+#endif
 	enable_cpc();
 
 #ifndef CONFIG_SYS_FSL_NO_SERDES

arch/powerpc/cpu/mpc85xx/start.S

@@ -122,7 +122,8 @@ _start_e500:
 #endif
 
 
-#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC)
+#if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_E500MC) && \
+	!defined(CONFIG_E6500)
 	/* ISBC uses L2 as stack.
 	 * Disable L2 cache here so that u-boot can enable it later
 	 * as part of it's normal flow

arch/powerpc/include/asm/fsl_secure_boot.h

@@ -17,5 +17,11 @@
 #endif
 #define CONFIG_SYS_PBI_FLASH_WINDOW		0xcff80000
 
+#if defined(CONFIG_B4860QDS)
+#define CONFIG_SYS_CPC_REINIT_F
+#undef CONFIG_SYS_INIT_L3_ADDR
+#define CONFIG_SYS_INIT_L3_ADDR			0xbff00000
+#endif
+
 #endif
 #endif

boards.cfg

@@ -744,6 +744,7 @@ Active  powerpc     mpc85xx        -           freescale       b4860qds
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_NAND                        B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4420QDS_SPIFLASH                    B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS                             B4860QDS:PPC_B4860                                                                                                                -
+Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SECURE_BOOT                 B4860QDS:PPC_B4860,SECURE_BOOT                                                                                                    Aneesh Bansal <aneesh.bansal@freescale.com>
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_NAND                        B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000                                                                      -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SPIFLASH                    B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000                                                                  -
 Active  powerpc     mpc85xx        -           freescale       b4860qds            B4860QDS_SRIO_PCIE_BOOT              B4860QDS:PPC_B4860,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000                                                                  -