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imx: cpu: move common chip revision id's

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Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revision

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
master
Adrian Alonso 10 years ago committed by Stefano Babic
parent e469719c8b
commit fc5ad4778d
5 changed files with 13 additions and 19 deletions
  1. 1
      arch/arm/cpu/arm926ejs/mx25/generic.c
  2. 12
      arch/arm/include/asm/arch-imx/cpu.h
  3. 4
      arch/arm/include/asm/arch-mx25/imx-regs.h
  4. 11
      arch/arm/include/asm/arch-mx5/imx-regs.h
  5. 4
      arch/arm/include/asm/arch-mx6/imx-regs.h

1
arch/arm/cpu/arm926ejs/mx25/generic.c
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@ -13,6 +13,7 @@
#include <div64.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>

12
arch/arm/include/asm/arch-imx/cpu.h
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@ -27,6 +27,18 @@
#define MXC_SOC_MX6 0x60
#define MXC_SOC_MX7 0x70
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
#define CHIP_REV_2_5 0x25
#define CHIP_REV_3_0 0x30
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
#define BOARD_VER_OFFSET 0x8
#define CS0_128 0
#define CS0_64M_CS1_64M 1
#define CS0_64M_CS1_32M_CS2_32M 2

4
arch/arm/include/asm/arch-mx25/imx-regs.h
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@ -526,8 +526,4 @@ struct cspi_regs {
IMX_CSPI2_BASE, \
IMX_CSPI3_BASE
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
#define CHIP_REV_1_2 0x12
#endif /* _IMX_REGS_H */

11
arch/arm/include/asm/arch-mx5/imx-regs.h
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@ -291,17 +291,6 @@
#define DP_MFD_216 (4 - 1)
#define DP_MFN_216 3
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
#define CHIP_REV_2_0 0x20
#define CHIP_REV_2_5 0x25
#define CHIP_REV_3_0 0x30
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
#define BOARD_VER_OFFSET 0x8
#define IMX_IIM_BASE (IIM_BASE_ADDR)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

4
arch/arm/include/asm/arch-mx6/imx-regs.h
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@ -325,10 +325,6 @@
#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \
MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR)
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_2 0x12
#define CHIP_REV_1_5 0x15
#define CHIP_REV_2_0 0x20
#if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL))
#define IRAM_SIZE 0x00040000
#else

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