@ -73,6 +73,8 @@ struct gen3_clk_priv {
struct clk clk_extal ;
struct clk clk_extalr ;
const struct rcar_gen3_cpg_pll_config * cpg_pll_config ;
const struct cpg_core_clk * core_clk ;
u32 core_clk_size ;
const struct mssr_mod_clk * mod_clk ;
u32 mod_clk_size ;
} ;
@ -181,7 +183,7 @@ enum clk_ids {
MOD_CLK_BASE
} ;
static const struct cpg_core_clk gen3 _core_clks[ ] = {
static const struct cpg_core_clk r8a7795 _core_clks[ ] = {
/* External Clock Inputs */
DEF_INPUT ( " extal " , CLK_EXTAL ) ,
DEF_INPUT ( " extalr " , CLK_EXTALR ) ,
@ -203,38 +205,38 @@ static const struct cpg_core_clk gen3_core_clks[] = {
DEF_FIXED ( " .sdsrc " , CLK_SDSRC , CLK_PLL1_DIV2 , 2 , 1 ) ,
/* Core Clock Outputs */
DEF_FIXED ( " ztr " , R8A7796 _CLK_ZTR , CLK_PLL1_DIV2 , 6 , 1 ) ,
DEF_FIXED ( " ztrd2 " , R8A7796 _CLK_ZTRD2 , CLK_PLL1_DIV2 , 12 , 1 ) ,
DEF_FIXED ( " zt " , R8A7796 _CLK_ZT , CLK_PLL1_DIV2 , 4 , 1 ) ,
DEF_FIXED ( " zx " , R8A7796 _CLK_ZX , CLK_PLL1_DIV2 , 2 , 1 ) ,
DEF_FIXED ( " s0d1 " , R8A7796 _CLK_S0D1 , CLK_S0 , 1 , 1 ) ,
DEF_FIXED ( " s0d2 " , R8A7796 _CLK_S0D2 , CLK_S0 , 2 , 1 ) ,
DEF_FIXED ( " s0d3 " , R8A7796 _CLK_S0D3 , CLK_S0 , 3 , 1 ) ,
DEF_FIXED ( " s0d4 " , R8A7796 _CLK_S0D4 , CLK_S0 , 4 , 1 ) ,
DEF_FIXED ( " s0d6 " , R8A7796 _CLK_S0D6 , CLK_S0 , 6 , 1 ) ,
DEF_FIXED ( " s0d8 " , R8A7796 _CLK_S0D8 , CLK_S0 , 8 , 1 ) ,
DEF_FIXED ( " s0d12 " , R8A7796 _CLK_S0D12 , CLK_S0 , 12 , 1 ) ,
DEF_FIXED ( " s1d1 " , R8A7796 _CLK_S1D1 , CLK_S1 , 1 , 1 ) ,
DEF_FIXED ( " s1d2 " , R8A7796 _CLK_S1D2 , CLK_S1 , 2 , 1 ) ,
DEF_FIXED ( " s1d4 " , R8A7796 _CLK_S1D4 , CLK_S1 , 4 , 1 ) ,
DEF_FIXED ( " s2d1 " , R8A7796 _CLK_S2D1 , CLK_S2 , 1 , 1 ) ,
DEF_FIXED ( " s2d2 " , R8A7796 _CLK_S2D2 , CLK_S2 , 2 , 1 ) ,
DEF_FIXED ( " s2d4 " , R8A7796 _CLK_S2D4 , CLK_S2 , 4 , 1 ) ,
DEF_FIXED ( " s3d1 " , R8A7796 _CLK_S3D1 , CLK_S3 , 1 , 1 ) ,
DEF_FIXED ( " s3d2 " , R8A7796 _CLK_S3D2 , CLK_S3 , 2 , 1 ) ,
DEF_FIXED ( " s3d4 " , R8A7796 _CLK_S3D4 , CLK_S3 , 4 , 1 ) ,
DEF_GEN3_SD ( " sd0 " , R8A7796 _CLK_SD0 , CLK_SDSRC , 0x074 ) ,
DEF_GEN3_SD ( " sd1 " , R8A7796 _CLK_SD1 , CLK_SDSRC , 0x078 ) ,
DEF_GEN3_SD ( " sd2 " , R8A7796 _CLK_SD2 , CLK_SDSRC , 0x268 ) ,
DEF_GEN3_SD ( " sd3 " , R8A7796 _CLK_SD3 , CLK_SDSRC , 0x26c ) ,
DEF_FIXED ( " cl " , R8A7796 _CLK_CL , CLK_PLL1_DIV2 , 48 , 1 ) ,
DEF_FIXED ( " cp " , R8A7796 _CLK_CP , CLK_EXTAL , 2 , 1 ) ,
DEF_FIXED ( " ztr " , R8A7795 _CLK_ZTR , CLK_PLL1_DIV2 , 6 , 1 ) ,
DEF_FIXED ( " ztrd2 " , R8A7795 _CLK_ZTRD2 , CLK_PLL1_DIV2 , 12 , 1 ) ,
DEF_FIXED ( " zt " , R8A7795 _CLK_ZT , CLK_PLL1_DIV2 , 4 , 1 ) ,
DEF_FIXED ( " zx " , R8A7795 _CLK_ZX , CLK_PLL1_DIV2 , 2 , 1 ) ,
DEF_FIXED ( " s0d1 " , R8A7795 _CLK_S0D1 , CLK_S0 , 1 , 1 ) ,
DEF_FIXED ( " s0d2 " , R8A7795 _CLK_S0D2 , CLK_S0 , 2 , 1 ) ,
DEF_FIXED ( " s0d3 " , R8A7795 _CLK_S0D3 , CLK_S0 , 3 , 1 ) ,
DEF_FIXED ( " s0d4 " , R8A7795 _CLK_S0D4 , CLK_S0 , 4 , 1 ) ,
DEF_FIXED ( " s0d6 " , R8A7795 _CLK_S0D6 , CLK_S0 , 6 , 1 ) ,
DEF_FIXED ( " s0d8 " , R8A7795 _CLK_S0D8 , CLK_S0 , 8 , 1 ) ,
DEF_FIXED ( " s0d12 " , R8A7795 _CLK_S0D12 , CLK_S0 , 12 , 1 ) ,
DEF_FIXED ( " s1d1 " , R8A7795 _CLK_S1D1 , CLK_S1 , 1 , 1 ) ,
DEF_FIXED ( " s1d2 " , R8A7795 _CLK_S1D2 , CLK_S1 , 2 , 1 ) ,
DEF_FIXED ( " s1d4 " , R8A7795 _CLK_S1D4 , CLK_S1 , 4 , 1 ) ,
DEF_FIXED ( " s2d1 " , R8A7795 _CLK_S2D1 , CLK_S2 , 1 , 1 ) ,
DEF_FIXED ( " s2d2 " , R8A7795 _CLK_S2D2 , CLK_S2 , 2 , 1 ) ,
DEF_FIXED ( " s2d4 " , R8A7795 _CLK_S2D4 , CLK_S2 , 4 , 1 ) ,
DEF_FIXED ( " s3d1 " , R8A7795 _CLK_S3D1 , CLK_S3 , 1 , 1 ) ,
DEF_FIXED ( " s3d2 " , R8A7795 _CLK_S3D2 , CLK_S3 , 2 , 1 ) ,
DEF_FIXED ( " s3d4 " , R8A7795 _CLK_S3D4 , CLK_S3 , 4 , 1 ) ,
DEF_GEN3_SD ( " sd0 " , R8A7795 _CLK_SD0 , CLK_SDSRC , 0x074 ) ,
DEF_GEN3_SD ( " sd1 " , R8A7795 _CLK_SD1 , CLK_SDSRC , 0x078 ) ,
DEF_GEN3_SD ( " sd2 " , R8A7795 _CLK_SD2 , CLK_SDSRC , 0x268 ) ,
DEF_GEN3_SD ( " sd3 " , R8A7795 _CLK_SD3 , CLK_SDSRC , 0x26c ) ,
DEF_FIXED ( " cl " , R8A7795 _CLK_CL , CLK_PLL1_DIV2 , 48 , 1 ) ,
DEF_FIXED ( " cp " , R8A7795 _CLK_CP , CLK_EXTAL , 2 , 1 ) ,
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
DEF_BASE ( " r " , R8A7796 _CLK_R , CLK_TYPE_GEN3_R , CLK_RINT ) ,
DEF_BASE ( " r " , R8A7795 _CLK_R , CLK_TYPE_GEN3_R , CLK_RINT ) ,
} ;
static const struct mssr_mod_clk r8a7795_mod_clks [ ] = {
@ -392,6 +394,62 @@ static const struct mssr_mod_clk r8a7795_mod_clks[] = {
DEF_MOD ( " scu-src0 " , 1031 , MOD_CLK_ID ( 1017 ) ) ,
} ;
static const struct cpg_core_clk r8a7796_core_clks [ ] = {
/* External Clock Inputs */
DEF_INPUT ( " extal " , CLK_EXTAL ) ,
DEF_INPUT ( " extalr " , CLK_EXTALR ) ,
/* Internal Core Clocks */
DEF_BASE ( " .main " , CLK_MAIN , CLK_TYPE_GEN3_MAIN , CLK_EXTAL ) ,
DEF_BASE ( " .pll0 " , CLK_PLL0 , CLK_TYPE_GEN3_PLL0 , CLK_MAIN ) ,
DEF_BASE ( " .pll1 " , CLK_PLL1 , CLK_TYPE_GEN3_PLL1 , CLK_MAIN ) ,
DEF_BASE ( " .pll2 " , CLK_PLL2 , CLK_TYPE_GEN3_PLL2 , CLK_MAIN ) ,
DEF_BASE ( " .pll3 " , CLK_PLL3 , CLK_TYPE_GEN3_PLL3 , CLK_MAIN ) ,
DEF_BASE ( " .pll4 " , CLK_PLL4 , CLK_TYPE_GEN3_PLL4 , CLK_MAIN ) ,
DEF_FIXED ( " .pll1_div2 " , CLK_PLL1_DIV2 , CLK_PLL1 , 2 , 1 ) ,
DEF_FIXED ( " .pll1_div4 " , CLK_PLL1_DIV4 , CLK_PLL1_DIV2 , 2 , 1 ) ,
DEF_FIXED ( " .s0 " , CLK_S0 , CLK_PLL1_DIV2 , 2 , 1 ) ,
DEF_FIXED ( " .s1 " , CLK_S1 , CLK_PLL1_DIV2 , 3 , 1 ) ,
DEF_FIXED ( " .s2 " , CLK_S2 , CLK_PLL1_DIV2 , 4 , 1 ) ,
DEF_FIXED ( " .s3 " , CLK_S3 , CLK_PLL1_DIV2 , 6 , 1 ) ,
DEF_FIXED ( " .sdsrc " , CLK_SDSRC , CLK_PLL1_DIV2 , 2 , 1 ) ,
/* Core Clock Outputs */
DEF_FIXED ( " ztr " , R8A7796_CLK_ZTR , CLK_PLL1_DIV2 , 6 , 1 ) ,
DEF_FIXED ( " ztrd2 " , R8A7796_CLK_ZTRD2 , CLK_PLL1_DIV2 , 12 , 1 ) ,
DEF_FIXED ( " zt " , R8A7796_CLK_ZT , CLK_PLL1_DIV2 , 4 , 1 ) ,
DEF_FIXED ( " zx " , R8A7796_CLK_ZX , CLK_PLL1_DIV2 , 2 , 1 ) ,
DEF_FIXED ( " s0d1 " , R8A7796_CLK_S0D1 , CLK_S0 , 1 , 1 ) ,
DEF_FIXED ( " s0d2 " , R8A7796_CLK_S0D2 , CLK_S0 , 2 , 1 ) ,
DEF_FIXED ( " s0d3 " , R8A7796_CLK_S0D3 , CLK_S0 , 3 , 1 ) ,
DEF_FIXED ( " s0d4 " , R8A7796_CLK_S0D4 , CLK_S0 , 4 , 1 ) ,
DEF_FIXED ( " s0d6 " , R8A7796_CLK_S0D6 , CLK_S0 , 6 , 1 ) ,
DEF_FIXED ( " s0d8 " , R8A7796_CLK_S0D8 , CLK_S0 , 8 , 1 ) ,
DEF_FIXED ( " s0d12 " , R8A7796_CLK_S0D12 , CLK_S0 , 12 , 1 ) ,
DEF_FIXED ( " s1d1 " , R8A7796_CLK_S1D1 , CLK_S1 , 1 , 1 ) ,
DEF_FIXED ( " s1d2 " , R8A7796_CLK_S1D2 , CLK_S1 , 2 , 1 ) ,
DEF_FIXED ( " s1d4 " , R8A7796_CLK_S1D4 , CLK_S1 , 4 , 1 ) ,
DEF_FIXED ( " s2d1 " , R8A7796_CLK_S2D1 , CLK_S2 , 1 , 1 ) ,
DEF_FIXED ( " s2d2 " , R8A7796_CLK_S2D2 , CLK_S2 , 2 , 1 ) ,
DEF_FIXED ( " s2d4 " , R8A7796_CLK_S2D4 , CLK_S2 , 4 , 1 ) ,
DEF_FIXED ( " s3d1 " , R8A7796_CLK_S3D1 , CLK_S3 , 1 , 1 ) ,
DEF_FIXED ( " s3d2 " , R8A7796_CLK_S3D2 , CLK_S3 , 2 , 1 ) ,
DEF_FIXED ( " s3d4 " , R8A7796_CLK_S3D4 , CLK_S3 , 4 , 1 ) ,
DEF_GEN3_SD ( " sd0 " , R8A7796_CLK_SD0 , CLK_SDSRC , 0x074 ) ,
DEF_GEN3_SD ( " sd1 " , R8A7796_CLK_SD1 , CLK_SDSRC , 0x078 ) ,
DEF_GEN3_SD ( " sd2 " , R8A7796_CLK_SD2 , CLK_SDSRC , 0x268 ) ,
DEF_GEN3_SD ( " sd3 " , R8A7796_CLK_SD3 , CLK_SDSRC , 0x26c ) ,
DEF_FIXED ( " cl " , R8A7796_CLK_CL , CLK_PLL1_DIV2 , 48 , 1 ) ,
DEF_FIXED ( " cp " , R8A7796_CLK_CP , CLK_EXTAL , 2 , 1 ) ,
/* NOTE: HDMI, CSI, CAN etc. clock are missing */
DEF_BASE ( " r " , R8A7796_CLK_R , CLK_TYPE_GEN3_R , CLK_RINT ) ,
} ;
static const struct mssr_mod_clk r8a7796_mod_clks [ ] = {
DEF_MOD ( " scif5 " , 202 , R8A7796_CLK_S3D4 ) ,
DEF_MOD ( " scif4 " , 203 , R8A7796_CLK_S3D4 ) ,
@ -648,17 +706,18 @@ static int gen3_clk_get_mod(struct clk *clk, const struct mssr_mod_clk **mssr)
static int gen3_clk_get_core ( struct clk * clk , const struct cpg_core_clk * * core )
{
struct gen3_clk_priv * priv = dev_get_priv ( clk - > dev ) ;
const unsigned long clkid = clk - > id & 0xffff ;
int i ;
if ( gen3_clk_is_mod ( clk ) )
return - EINVAL ;
for ( i = 0 ; i < ARRAY_SIZE ( gen3_core_clks ) ; i + + ) {
if ( gen3_core_clks [ i ] . id ! = clkid )
for ( i = 0 ; i < priv - > core_clk_size ; i + + ) {
if ( priv - > core_clk [ i ] . id ! = clkid )
continue ;
* core = & gen3_core_clks [ i ] ;
* core = & priv - > core_clk [ i ] ;
return 0 ;
}
@ -895,6 +954,8 @@ static int gen3_clk_probe(struct udevice *dev)
switch ( model ) {
case CLK_R8A7795 :
priv - > core_clk = r8a7795_core_clks ;
priv - > core_clk_size = ARRAY_SIZE ( r8a7795_core_clks ) ;
priv - > mod_clk = r8a7795_mod_clks ;
priv - > mod_clk_size = ARRAY_SIZE ( r8a7795_mod_clks ) ;
ret = fdt_node_offset_by_compatible ( gd - > fdt_blob , - 1 ,
@ -903,6 +964,8 @@ static int gen3_clk_probe(struct udevice *dev)
return ret ;
break ;
case CLK_R8A7796 :
priv - > core_clk = r8a7796_core_clks ;
priv - > core_clk_size = ARRAY_SIZE ( r8a7796_core_clks ) ;
priv - > mod_clk = r8a7796_mod_clks ;
priv - > mod_clk_size = ARRAY_SIZE ( r8a7796_mod_clks ) ;
ret = fdt_node_offset_by_compatible ( gd - > fdt_blob , - 1 ,