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Exynos Display port controller |
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============================== |
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|
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Required properties: |
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SOC specific: |
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compatible: should be "samsung,exynos5-dp" |
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reg: Base address of DP IP |
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|
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Optional properties: |
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samsung,h-res: X resolution of the panel |
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samsung,h-sync-width: hsync value |
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samsung,h-back-porch: left margin |
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samsung,h-front-porch right margin |
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samsung,v-res: Y resolution of the panel |
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samsung,v-sync-width: vsync value |
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samsung,v-back-porch: upper margin |
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samsung,v-front-porch: lower margin |
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samsung,v-sync-rate: refresh rate |
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|
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samsung,lt-status: Link training status |
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0(DP_LT_NONE), 1(DP_LT_START), 2(DP_LT_CR), 3(DP_LT_ET), |
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4(DP_LT_FINISHED), 5(DP_LT_FAIL) |
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|
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samsung,master-mode: 1 if you want to run DP as master, else 0 |
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samsung,bist-mode: 1 to enable video bist mode, else 0 |
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samsung,bist-pattern: bist mode pattern type |
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0(NO_PATTERN), 1(COLOR_RAMP), 2(BALCK_WHITE_V_LINES), |
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3(COLOR_SQUARE), 4(INVALID_PATTERN), 5(COLORBAR_32), |
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6(COLORBAR_64),7(WHITE_GRAY_BALCKBAR_32), |
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8(WHITE_GRAY_BALCKBAR_64),9(MOBILE_WHITEBAR_32), |
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10(MOBILE_WHITEBAR_64) |
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samsung,h-sync-polarity: Horizontal Sync polarity |
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CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH |
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samsung,v-sync-polarity: Vertical Sync polarity |
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CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH |
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samsung,interlaced: Progressive if 0, else Interlaced |
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samsung,color-space: input video data format |
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COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2 |
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samsung,dynamic-range: dynamic range for input video data |
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VESA = 0, CEA = 1 |
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samsung,ycbcr-coeff: YCbCr co-efficients for input video |
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COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1 |
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samsung,color-depth: number of bits per colour component |
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COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3 |
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|
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Example: |
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SOC specific part: |
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dp@145b0000 { |
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compatible = "samsung,exynos5-dp"; |
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reg = <0x145b0000 0x1000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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|
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Board(panel) specific part: |
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dp@145b0000 { |
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samsung,lt-status = <0>; |
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|
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samsung,master-mode = <0>; |
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samsung,bist-mode = <0>; |
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samsung,bist-pattern = <0>; |
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samsung,h-sync-polarity = <0>; |
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samsung,v-sync-polarity = <0>; |
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samsung,interlaced = <0>; |
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samsung,color-space = <0>; |
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samsung,dynamic-range = <0>; |
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samsung,ycbcr-coeff = <0>; |
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samsung,color-depth = <1>; |
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}; |
@ -0,0 +1,92 @@ |
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Exynos Display Controller |
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========================= |
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Required properties: |
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SOC specific: |
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compatible: should be "samsung,exynos-fimd" |
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reg: Base address of FIMD IP. |
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|
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Board(panel specific): |
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samsung,vl-col: X resolution of the panel |
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samsung,vl-row: Y resolution of the panel |
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samsung,vl-freq: Refresh rate |
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samsung,vl-bpix: Bits per pixel |
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samsung,vl-hspw: Hsync value |
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samsung,vl-hfpd: Right margin |
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samsung,vl-hbpd: Left margin |
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samsung,vl-vspw: Vsync value |
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samsung,vl-vfpd: Lower margin |
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samsung,vl-vbpd: Upper margin |
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|
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Optional properties: |
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Board(panel specific): |
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samsung,vl-width: width of display area in mm |
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samsung,vl-height: Height of display area in mm |
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|
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samsung,vl-clkp: Clock polarity |
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CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH |
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samsung,vl-oep: Output Enable polarity |
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CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH |
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samsung,vl-hsp: Horizontal Sync polarity |
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CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH |
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samsung,vl-vsp: Vertical Sync polarity |
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CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH |
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samsung,vl-dp: Data polarity |
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CONFIG_SYS_LOW if defined, else CONFIG_SYS_HIGH |
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|
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samsung,vl-cmd-allow-len: Wait end of frame |
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samsung,winid: Window number on which data is to be displayed |
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samsung,init-delay: Delay before LCD initialization starts |
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samsung,power-on-delay: Delay after LCD is powered on |
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samsung,reset-delay: Delay after LCD is reset |
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samsung,interface-mode: 1(FIMD_RGB_INTERFACE), 2(FIMD_CPU_INTERFACE) |
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samsung,mipi-enabled: 1 if you want to use MIPI, else 0 |
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samsung,dp-enabled: 1is you want to use DP, else 0 |
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samsung,cs-setup: cs_setup value in FIMD_CPU_INTERFACE mode. |
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samsung,wr-setup: wr_setup value in FIMD_CPU_INTERFACE mode. |
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samsung,wr-act: wr_act value in FIMD_CPU_INTERFACE mode. |
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samsung,wr-hold: wr_hold value in FIMD_CPU_INTERFACE mode. |
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samsung,logo-on: 1 if you want to use custom logo. |
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0 if you want LCD console. |
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samsung,logo-width: pixel width of logo image. Valid if logo_on = 1 |
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samsung,logo-height: pixel height of logo image. Valid if logo_on = 1 |
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samsung,logo-addr: Address of logo image. Valid if logo_on = 1 |
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samsung,rgb-mode: 0(MODE_RGB_P), 1(MODE_BGR_P), |
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2(MODE_RGB_S), 3(MODE_BGR_S) |
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samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL) |
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samsung,sclk-div: parent_clock/source_clock ratio |
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samsung,dual-lcd-enabled: 1 if you support two LCD, else 0 |
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Example: |
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SOC specific part: |
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fimd@14400000 { |
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compatible = "samsung,exynos-fimd"; |
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reg = <0x14400000 0x10000>; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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}; |
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Board specific part: |
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fimd@14400000 { |
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samsung,vl-freq = <60>; |
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samsung,vl-col = <2560>; |
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samsung,vl-row = <1600>; |
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samsung,vl-width = <2560>; |
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samsung,vl-height = <1600>; |
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samsung,vl-clkp; |
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samsung,vl-dp; |
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samsung,vl-bpix = <4>; |
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samsung,vl-hspw = <32>; |
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samsung,vl-hbpd = <80>; |
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samsung,vl-hfpd = <48>; |
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samsung,vl-vspw = <6>; |
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samsung,vl-vbpd = <37>; |
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samsung,vl-vfpd = <3>; |
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samsung,vl-cmd-allow-len = <0xf>; |
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samsung,winid = <3>; |
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samsung,interface-mode = <1>; |
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samsung,dp-enabled = <1>; |
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samsung,dual-lcd-enabled = <0>; |
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}; |
@ -0,0 +1,47 @@ |
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#
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# Copyright (c) 2013 Samsung Electronics Co., Ltd.
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# http://www.samsung.com
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
|
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
|
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
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#
|
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# You should have received a copy of the GNU General Public License
|
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# along with this program; if not, write to the Free Software
|
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk |
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LIB := $(obj)libcrypto.o
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COBJS-$(CONFIG_EXYNOS_ACE_SHA) += ace_sha.o
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COBJS := $(COBJS-y)
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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all: $(LIB) |
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$(LIB): $(obj).depend $(OBJS) |
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$(call cmd_link_o_target, $(OBJS))
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk |
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sinclude $(obj).depend |
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########################################################################
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@ -0,0 +1,126 @@ |
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/*
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* Advanced Crypto Engine - SHA Firmware |
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* Copyright (c) 2012 Samsung Electronics |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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#include <common.h> |
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#include <sha256.h> |
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#include <sha1.h> |
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#include <asm/errno.h> |
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#include "ace_sha.h" |
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/* SHA1 value for the message of zero length */ |
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static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = { |
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0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D, |
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0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90, |
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0xAF, 0xD8, 0x07, 0x09}; |
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/* SHA256 value for the message of zero length */ |
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static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = { |
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0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14, |
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0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24, |
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0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C, |
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0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55}; |
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int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len, |
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unsigned char *pout, unsigned int hash_type) |
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{ |
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unsigned int i, reg, len; |
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unsigned int *pdigest; |
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struct exynos_ace_sfr *ace_sha_reg = |
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(struct exynos_ace_sfr *)samsung_get_base_ace_sfr(); |
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if (buf_len == 0) { |
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/* ACE H/W cannot compute hash value for empty string */ |
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if (hash_type == ACE_SHA_TYPE_SHA1) |
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memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN); |
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else |
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memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN); |
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return 0; |
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} |
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|
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/* Flush HRDMA */ |
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writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac); |
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writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac); |
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|
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/* Set byte swap of data in */ |
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writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON, |
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&ace_sha_reg->hash_byteswap); |
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|
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/* Select Hash input mux as external source */ |
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reg = readl(&ace_sha_reg->fc_fifoctrl); |
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reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT; |
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writel(reg, &ace_sha_reg->fc_fifoctrl); |
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|
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/* Set Hash as SHA1 or SHA256 and start Hash engine */ |
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reg = (hash_type == ACE_SHA_TYPE_SHA1) ? |
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ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH; |
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reg |= ACE_HASH_STARTBIT_ON; |
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writel(reg, &ace_sha_reg->hash_control); |
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|
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/* Enable FIFO mode */ |
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writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode); |
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|
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/* Set message length */ |
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writel(buf_len, &ace_sha_reg->hash_msgsize_low); |
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writel(0, &ace_sha_reg->hash_msgsize_high); |
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|
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/* Set HRDMA */ |
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writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas); |
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writel(buf_len, &ace_sha_reg->fc_hrdmal); |
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|
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while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) == |
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ACE_HASH_MSGDONE_OFF) { |
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/*
|
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* PRNG error bit goes HIGH if a PRNG request occurs without |
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* a complete seed setup. We are using this bit to check h/w |
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* fault because proper setup is not expected in that case. |
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*/ |
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if ((readl(&ace_sha_reg->hash_status) |
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& ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON) |
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return -EBUSY; |
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} |
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|
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/* Clear MSG_DONE bit */ |
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writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status); |
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/* Read hash result */ |
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pdigest = (unsigned int *)pout; |
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len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN; |
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for (i = 0; i < len / 4; i++) |
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pdigest[i] = readl(&ace_sha_reg->hash_result[i]); |
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|
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/* Clear HRDMA pending bit */ |
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writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend); |
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return 0; |
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} |
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|
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void hw_sha256(const unsigned char *pbuf, unsigned int buf_len, |
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unsigned char *pout, unsigned int chunk_size) |
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{ |
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if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256)) |
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debug("ACE was not setup properly or it is faulty\n"); |
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} |
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|
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void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, |
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unsigned char *pout, unsigned int chunk_size) |
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{ |
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if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1)) |
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debug("ACE was not setup properly or it is faulty\n"); |
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} |
@ -0,0 +1,325 @@ |
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/*
|
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* Header file for Advanced Crypto Engine - SFR definitions |
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* |
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* Copyright (c) 2012 Samsung Electronics |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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* |
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*/ |
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|
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#ifndef __ACE_SHA_H |
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#define __ACE_SHA_H |
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|
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struct exynos_ace_sfr { |
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unsigned int fc_intstat; /* base + 0 */ |
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unsigned int fc_intenset; |
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unsigned int fc_intenclr; |
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unsigned int fc_intpend; |
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unsigned int fc_fifostat; |
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unsigned int fc_fifoctrl; |
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unsigned int fc_global; |
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unsigned int res1; |
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unsigned int fc_brdmas; |
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unsigned int fc_brdmal; |
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unsigned int fc_brdmac; |
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unsigned int res2; |
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unsigned int fc_btdmas; |
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unsigned int fc_btdmal; |
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unsigned int fc_btdmac; |
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unsigned int res3; |
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unsigned int fc_hrdmas; |
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unsigned int fc_hrdmal; |
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unsigned int fc_hrdmac; |
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unsigned int res4; |
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unsigned int fc_pkdmas; |
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unsigned int fc_pkdmal; |
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unsigned int fc_pkdmac; |
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unsigned int fc_pkdmao; |
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unsigned char res5[0x1a0]; |
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|
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unsigned int aes_control; /* base + 0x200 */ |
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unsigned int aes_status; |
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unsigned char res6[0x8]; |
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unsigned int aes_in[4]; |
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unsigned int aes_out[4]; |
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unsigned int aes_iv[4]; |
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unsigned int aes_cnt[4]; |
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unsigned char res7[0x30]; |
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unsigned int aes_key[8]; |
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unsigned char res8[0x60]; |
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|
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unsigned int tdes_control; /* base + 0x300 */ |
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unsigned int tdes_status; |
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unsigned char res9[0x8]; |
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unsigned int tdes_key[6]; |
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unsigned int tdes_iv[2]; |
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unsigned int tdes_in[2]; |
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unsigned int tdes_out[2]; |
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unsigned char res10[0xc0]; |
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|
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unsigned int hash_control; /* base + 0x400 */ |
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unsigned int hash_control2; |
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unsigned int hash_fifo_mode; |
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unsigned int hash_byteswap; |
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unsigned int hash_status; |
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unsigned char res11[0xc]; |
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unsigned int hash_msgsize_low; |
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unsigned int hash_msgsize_high; |
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unsigned int hash_prelen_low; |
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unsigned int hash_prelen_high; |
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unsigned int hash_in[16]; |
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unsigned int hash_key_in[16]; |
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unsigned int hash_iv[8]; |
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unsigned char res12[0x30]; |
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unsigned int hash_result[8]; |
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unsigned char res13[0x20]; |
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unsigned int hash_seed[8]; |
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unsigned int hash_prng[8]; |
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unsigned char res14[0x180]; |
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|
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unsigned int pka_sfr[5]; /* base + 0x700 */ |
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}; |
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|
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/* ACE_FC_INT */ |
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#define ACE_FC_PKDMA (1 << 0) |
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#define ACE_FC_HRDMA (1 << 1) |
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#define ACE_FC_BTDMA (1 << 2) |
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#define ACE_FC_BRDMA (1 << 3) |
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#define ACE_FC_PRNG_ERROR (1 << 4) |
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#define ACE_FC_MSG_DONE (1 << 5) |
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#define ACE_FC_PRNG_DONE (1 << 6) |
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#define ACE_FC_PARTIAL_DONE (1 << 7) |
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|
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/* ACE_FC_FIFOSTAT */ |
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#define ACE_FC_PKFIFO_EMPTY (1 << 0) |
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#define ACE_FC_PKFIFO_FULL (1 << 1) |
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#define ACE_FC_HRFIFO_EMPTY (1 << 2) |
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#define ACE_FC_HRFIFO_FULL (1 << 3) |
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#define ACE_FC_BTFIFO_EMPTY (1 << 4) |
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#define ACE_FC_BTFIFO_FULL (1 << 5) |
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#define ACE_FC_BRFIFO_EMPTY (1 << 6) |
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#define ACE_FC_BRFIFO_FULL (1 << 7) |
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|
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/* ACE_FC_FIFOCTRL */ |
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#define ACE_FC_SELHASH_MASK (3 << 0) |
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#define ACE_FC_SELHASH_EXOUT (0 << 0) /* independent source */ |
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#define ACE_FC_SELHASH_BCIN (1 << 0) /* blk cipher input */ |
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#define ACE_FC_SELHASH_BCOUT (2 << 0) /* blk cipher output */ |
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#define ACE_FC_SELBC_MASK (1 << 2) |
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#define ACE_FC_SELBC_AES (0 << 2) |
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#define ACE_FC_SELBC_DES (1 << 2) |
||||
|
||||
/* ACE_FC_GLOBAL */ |
||||
#define ACE_FC_SSS_RESET (1 << 0) |
||||
#define ACE_FC_DMA_RESET (1 << 1) |
||||
#define ACE_FC_AES_RESET (1 << 2) |
||||
#define ACE_FC_DES_RESET (1 << 3) |
||||
#define ACE_FC_HASH_RESET (1 << 4) |
||||
#define ACE_FC_AXI_ENDIAN_MASK (3 << 6) |
||||
#define ACE_FC_AXI_ENDIAN_LE (0 << 6) |
||||
#define ACE_FC_AXI_ENDIAN_BIBE (1 << 6) |
||||
#define ACE_FC_AXI_ENDIAN_WIBE (2 << 6) |
||||
|
||||
/* Feed control - BRDMA control */ |
||||
#define ACE_FC_BRDMACFLUSH_OFF (0 << 0) |
||||
#define ACE_FC_BRDMACFLUSH_ON (1 << 0) |
||||
#define ACE_FC_BRDMACSWAP_ON (1 << 1) |
||||
#define ACE_FC_BRDMACARPROT_MASK (0x7 << 2) |
||||
#define ACE_FC_BRDMACARPROT_OFS 2 |
||||
#define ACE_FC_BRDMACARCACHE_MASK (0xf << 5) |
||||
#define ACE_FC_BRDMACARCACHE_OFS 5 |
||||
|
||||
/* Feed control - BTDMA control */ |
||||
#define ACE_FC_BTDMACFLUSH_OFF (0 << 0) |
||||
#define ACE_FC_BTDMACFLUSH_ON (1 << 0) |
||||
#define ACE_FC_BTDMACSWAP_ON (1 << 1) |
||||
#define ACE_FC_BTDMACAWPROT_MASK (0x7 << 2) |
||||
#define ACE_FC_BTDMACAWPROT_OFS 2 |
||||
#define ACE_FC_BTDMACAWCACHE_MASK (0xf << 5) |
||||
#define ACE_FC_BTDMACAWCACHE_OFS 5 |
||||
|
||||
/* Feed control - HRDMA control */ |
||||
#define ACE_FC_HRDMACFLUSH_OFF (0 << 0) |
||||
#define ACE_FC_HRDMACFLUSH_ON (1 << 0) |
||||
#define ACE_FC_HRDMACSWAP_ON (1 << 1) |
||||
#define ACE_FC_HRDMACARPROT_MASK (0x7 << 2) |
||||
#define ACE_FC_HRDMACARPROT_OFS 2 |
||||
#define ACE_FC_HRDMACARCACHE_MASK (0xf << 5) |
||||
#define ACE_FC_HRDMACARCACHE_OFS 5 |
||||
|
||||
/* Feed control - PKDMA control */ |
||||
#define ACE_FC_PKDMACBYTESWAP_ON (1 << 3) |
||||
#define ACE_FC_PKDMACDESEND_ON (1 << 2) |
||||
#define ACE_FC_PKDMACTRANSMIT_ON (1 << 1) |
||||
#define ACE_FC_PKDMACFLUSH_ON (1 << 0) |
||||
|
||||
/* Feed control - PKDMA offset */ |
||||
#define ACE_FC_SRAMOFFSET_MASK 0xfff |
||||
|
||||
/* AES control */ |
||||
#define ACE_AES_MODE_MASK (1 << 0) |
||||
#define ACE_AES_MODE_ENC (0 << 0) |
||||
#define ACE_AES_MODE_DEC (1 << 0) |
||||
#define ACE_AES_OPERMODE_MASK (3 << 1) |
||||
#define ACE_AES_OPERMODE_ECB (0 << 1) |
||||
#define ACE_AES_OPERMODE_CBC (1 << 1) |
||||
#define ACE_AES_OPERMODE_CTR (2 << 1) |
||||
#define ACE_AES_FIFO_MASK (1 << 3) |
||||
#define ACE_AES_FIFO_OFF (0 << 3) /* CPU mode */ |
||||
#define ACE_AES_FIFO_ON (1 << 3) /* FIFO mode */ |
||||
#define ACE_AES_KEYSIZE_MASK (3 << 4) |
||||
#define ACE_AES_KEYSIZE_128 (0 << 4) |
||||
#define ACE_AES_KEYSIZE_192 (1 << 4) |
||||
#define ACE_AES_KEYSIZE_256 (2 << 4) |
||||
#define ACE_AES_KEYCNGMODE_MASK (1 << 6) |
||||
#define ACE_AES_KEYCNGMODE_OFF (0 << 6) |
||||
#define ACE_AES_KEYCNGMODE_ON (1 << 6) |
||||
#define ACE_AES_SWAP_MASK (0x1f << 7) |
||||
#define ACE_AES_SWAPKEY_OFF (0 << 7) |
||||
#define ACE_AES_SWAPKEY_ON (1 << 7) |
||||
#define ACE_AES_SWAPCNT_OFF (0 << 8) |
||||
#define ACE_AES_SWAPCNT_ON (1 << 8) |
||||
#define ACE_AES_SWAPIV_OFF (0 << 9) |
||||
#define ACE_AES_SWAPIV_ON (1 << 9) |
||||
#define ACE_AES_SWAPDO_OFF (0 << 10) |
||||
#define ACE_AES_SWAPDO_ON (1 << 10) |
||||
#define ACE_AES_SWAPDI_OFF (0 << 11) |
||||
#define ACE_AES_SWAPDI_ON (1 << 11) |
||||
#define ACE_AES_COUNTERSIZE_MASK (3 << 12) |
||||
#define ACE_AES_COUNTERSIZE_128 (0 << 12) |
||||
#define ACE_AES_COUNTERSIZE_64 (1 << 12) |
||||
#define ACE_AES_COUNTERSIZE_32 (2 << 12) |
||||
#define ACE_AES_COUNTERSIZE_16 (3 << 12) |
||||
|
||||
/* AES status */ |
||||
#define ACE_AES_OUTRDY_MASK (1 << 0) |
||||
#define ACE_AES_OUTRDY_OFF (0 << 0) |
||||
#define ACE_AES_OUTRDY_ON (1 << 0) |
||||
#define ACE_AES_INRDY_MASK (1 << 1) |
||||
#define ACE_AES_INRDY_OFF (0 << 1) |
||||
#define ACE_AES_INRDY_ON (1 << 1) |
||||
#define ACE_AES_BUSY_MASK (1 << 2) |
||||
#define ACE_AES_BUSY_OFF (0 << 2) |
||||
#define ACE_AES_BUSY_ON (1 << 2) |
||||
|
||||
/* TDES control */ |
||||
#define ACE_TDES_MODE_MASK (1 << 0) |
||||
#define ACE_TDES_MODE_ENC (0 << 0) |
||||
#define ACE_TDES_MODE_DEC (1 << 0) |
||||
#define ACE_TDES_OPERMODE_MASK (1 << 1) |
||||
#define ACE_TDES_OPERMODE_ECB (0 << 1) |
||||
#define ACE_TDES_OPERMODE_CBC (1 << 1) |
||||
#define ACE_TDES_SEL_MASK (3 << 3) |
||||
#define ACE_TDES_SEL_DES (0 << 3) |
||||
#define ACE_TDES_SEL_TDESEDE (1 << 3) /* TDES EDE mode */ |
||||
#define ACE_TDES_SEL_TDESEEE (3 << 3) /* TDES EEE mode */ |
||||
#define ACE_TDES_FIFO_MASK (1 << 5) |
||||
#define ACE_TDES_FIFO_OFF (0 << 5) /* CPU mode */ |
||||
#define ACE_TDES_FIFO_ON (1 << 5) /* FIFO mode */ |
||||
#define ACE_TDES_SWAP_MASK (0xf << 6) |
||||
#define ACE_TDES_SWAPKEY_OFF (0 << 6) |
||||
#define ACE_TDES_SWAPKEY_ON (1 << 6) |
||||
#define ACE_TDES_SWAPIV_OFF (0 << 7) |
||||
#define ACE_TDES_SWAPIV_ON (1 << 7) |
||||
#define ACE_TDES_SWAPDO_OFF (0 << 8) |
||||
#define ACE_TDES_SWAPDO_ON (1 << 8) |
||||
#define ACE_TDES_SWAPDI_OFF (0 << 9) |
||||
#define ACE_TDES_SWAPDI_ON (1 << 9) |
||||
|
||||
/* TDES status */ |
||||
#define ACE_TDES_OUTRDY_MASK (1 << 0) |
||||
#define ACE_TDES_OUTRDY_OFF (0 << 0) |
||||
#define ACE_TDES_OUTRDY_ON (1 << 0) |
||||
#define ACE_TDES_INRDY_MASK (1 << 1) |
||||
#define ACE_TDES_INRDY_OFF (0 << 1) |
||||
#define ACE_TDES_INRDY_ON (1 << 1) |
||||
#define ACE_TDES_BUSY_MASK (1 << 2) |
||||
#define ACE_TDES_BUSY_OFF (0 << 2) |
||||
#define ACE_TDES_BUSY_ON (1 << 2) |
||||
|
||||
/* Hash control */ |
||||
#define ACE_HASH_ENGSEL_MASK (0xf << 0) |
||||
#define ACE_HASH_ENGSEL_SHA1HASH (0x0 << 0) |
||||
#define ACE_HASH_ENGSEL_SHA1HMAC (0x1 << 0) |
||||
#define ACE_HASH_ENGSEL_SHA1HMACIN (0x1 << 0) |
||||
#define ACE_HASH_ENGSEL_SHA1HMACOUT (0x9 << 0) |
||||
#define ACE_HASH_ENGSEL_MD5HASH (0x2 << 0) |
||||
#define ACE_HASH_ENGSEL_MD5HMAC (0x3 << 0) |
||||
#define ACE_HASH_ENGSEL_MD5HMACIN (0x3 << 0) |
||||
#define ACE_HASH_ENGSEL_MD5HMACOUT (0xb << 0) |
||||
#define ACE_HASH_ENGSEL_SHA256HASH (0x4 << 0) |
||||
#define ACE_HASH_ENGSEL_SHA256HMAC (0x5 << 0) |
||||
#define ACE_HASH_ENGSEL_PRNG (0x8 << 0) |
||||
#define ACE_HASH_STARTBIT_ON (1 << 4) |
||||
#define ACE_HASH_USERIV_EN (1 << 5) |
||||
#define ACE_HASH_PAUSE_ON (1 << 0) |
||||
|
||||
/* Hash control - FIFO mode */ |
||||
#define ACE_HASH_FIFO_MASK (1 << 0) |
||||
#define ACE_HASH_FIFO_OFF (0 << 0) |
||||
#define ACE_HASH_FIFO_ON (1 << 0) |
||||
|
||||
/* Hash control - byte swap */ |
||||
#define ACE_HASH_SWAP_MASK (0xf << 0) |
||||
#define ACE_HASH_SWAPKEY_OFF (0 << 0) |
||||
#define ACE_HASH_SWAPKEY_ON (1 << 0) |
||||
#define ACE_HASH_SWAPIV_OFF (0 << 1) |
||||
#define ACE_HASH_SWAPIV_ON (1 << 1) |
||||
#define ACE_HASH_SWAPDO_OFF (0 << 2) |
||||
#define ACE_HASH_SWAPDO_ON (1 << 2) |
||||
#define ACE_HASH_SWAPDI_OFF (0 << 3) |
||||
#define ACE_HASH_SWAPDI_ON (1 << 3) |
||||
|
||||
/* Hash status */ |
||||
#define ACE_HASH_BUFRDY_MASK (1 << 0) |
||||
#define ACE_HASH_BUFRDY_OFF (0 << 0) |
||||
#define ACE_HASH_BUFRDY_ON (1 << 0) |
||||
#define ACE_HASH_SEEDSETTING_MASK (1 << 1) |
||||
#define ACE_HASH_SEEDSETTING_OFF (0 << 1) |
||||
#define ACE_HASH_SEEDSETTING_ON (1 << 1) |
||||
#define ACE_HASH_PRNGBUSY_MASK (1 << 2) |
||||
#define ACE_HASH_PRNGBUSY_OFF (0 << 2) |
||||
#define ACE_HASH_PRNGBUSY_ON (1 << 2) |
||||
#define ACE_HASH_PARTIALDONE_MASK (1 << 4) |
||||
#define ACE_HASH_PARTIALDONE_OFF (0 << 4) |
||||
#define ACE_HASH_PARTIALDONE_ON (1 << 4) |
||||
#define ACE_HASH_PRNGDONE_MASK (1 << 5) |
||||
#define ACE_HASH_PRNGDONE_OFF (0 << 5) |
||||
#define ACE_HASH_PRNGDONE_ON (1 << 5) |
||||
#define ACE_HASH_MSGDONE_MASK (1 << 6) |
||||
#define ACE_HASH_MSGDONE_OFF (0 << 6) |
||||
#define ACE_HASH_MSGDONE_ON (1 << 6) |
||||
#define ACE_HASH_PRNGERROR_MASK (1 << 7) |
||||
#define ACE_HASH_PRNGERROR_OFF (0 << 7) |
||||
#define ACE_HASH_PRNGERROR_ON (1 << 7) |
||||
|
||||
#define ACE_SHA_TYPE_SHA1 1 |
||||
#define ACE_SHA_TYPE_SHA256 2 |
||||
|
||||
/**
|
||||
* Computes hash value of input pbuf using ACE |
||||
* |
||||
* @param in_addr A pointer to the input buffer |
||||
* @param bufleni Byte length of input buffer |
||||
* @param out_addr A pointer to the output buffer. When complete |
||||
* 32 bytes are copied to pout[0]...pout[31]. Thus, a user |
||||
* should allocate at least 32 bytes at pOut in advance. |
||||
* @param hash_type SHA1 or SHA256 |
||||
* |
||||
* @return 0 on Success, -1 on Failure (Timeout) |
||||
*/ |
||||
int ace_sha_hash_digest(const uchar * in_addr, uint buflen, |
||||
uchar * out_addr, uint hash_type); |
||||
#endif |
@ -0,0 +1,50 @@ |
||||
/*
|
||||
* Header file for SHA hardware acceleration |
||||
* |
||||
* Copyright (c) 2012 Samsung Electronics |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
#ifndef __HW_SHA_H |
||||
#define __HW_SHA_H |
||||
|
||||
|
||||
/**
|
||||
* Computes hash value of input pbuf using h/w acceleration |
||||
* |
||||
* @param in_addr A pointer to the input buffer |
||||
* @param bufleni Byte length of input buffer |
||||
* @param out_addr A pointer to the output buffer. When complete |
||||
* 32 bytes are copied to pout[0]...pout[31]. Thus, a user |
||||
* should allocate at least 32 bytes at pOut in advance. |
||||
* @param chunk_size chunk size for sha256 |
||||
*/ |
||||
void hw_sha256(const uchar * in_addr, uint buflen, |
||||
uchar * out_addr, uint chunk_size); |
||||
|
||||
/**
|
||||
* Computes hash value of input pbuf using h/w acceleration |
||||
* |
||||
* @param in_addr A pointer to the input buffer |
||||
* @param bufleni Byte length of input buffer |
||||
* @param out_addr A pointer to the output buffer. When complete |
||||
* 32 bytes are copied to pout[0]...pout[31]. Thus, a user |
||||
* should allocate at least 32 bytes at pOut in advance. |
||||
* @param chunk_size chunk_size for sha1 |
||||
*/ |
||||
void hw_sha1(const uchar * in_addr, uint buflen, |
||||
uchar * out_addr, uint chunk_size); |
||||
#endif |
Loading…
Reference in new issue