* 'master' of git://git.denx.de/u-boot-video: video: atmel/lcd: add LCD driver for new Atmel SoC video: cfb_console: flush dcache for frame buffer in DRAM cfb_console: Ignore bell character cfb_console: Add console_clear_line function cfb_console: Fix function console_back omap3_dss: cosmetic changes omap3_dss: add optional framebuffer mx53loco: Add LCD support mx5: Rename mx51_fb_init() mx53: Allow IPUv3 driver to also work on mx53 mx51evk: Add LCD support EXYNOS: display 32bpp bitmap TIZEN logo create lib/tizen directory LCD: display 32bpp decompressed bitmap image common/lcd.c: reduce one CONFIG_LCD_LOGO ifdef common/lcd.c: reduce some CONFIG_LCD_*_LOGO ifdefs common/lcd.c: use ARRAY_SIZE cmd_bmp.c: make bmp_display() usable by drivers or board code LCD: support another s6e8ax0 panel type LCD: change s6e8ax0 panel gamma value include/video.h: drop unused video_printf() Signed-off-by: Wolfgang Denk <wd@denx.de>master
Wolfgang Denk
12 years ago
commit
fedab338f3
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/*
|
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* Driver for AT91/AT32 MULTI LAYER LCD Controller |
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* |
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* Copyright (C) 2012 Atmel Corporation |
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* |
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* See file CREDITS for list of people who contributed to this |
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* project. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation; either version 2 of |
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* the License, or (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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* MA 02111-1307 USA |
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*/ |
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|
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#include <common.h> |
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#include <asm/io.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/arch/clk.h> |
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#include <lcd.h> |
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#include <atmel_hlcdc.h> |
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int lcd_line_length; |
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int lcd_color_fg; |
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int lcd_color_bg; |
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void *lcd_base; /* Start of framebuffer memory */ |
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void *lcd_console_address; /* Start of console buffer */ |
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short console_col; |
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short console_row; |
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/* configurable parameters */ |
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#define ATMEL_LCDC_CVAL_DEFAULT 0xc8 |
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#define ATMEL_LCDC_DMA_BURST_LEN 8 |
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#ifndef ATMEL_LCDC_GUARD_TIME |
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#define ATMEL_LCDC_GUARD_TIME 1 |
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#endif |
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#define ATMEL_LCDC_FIFO_SIZE 512 |
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#define lcdc_readl(reg) __raw_readl((reg)) |
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#define lcdc_writel(reg, val) __raw_writel((val), (reg)) |
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void lcd_ctrl_init(void *lcdbase) |
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{ |
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unsigned long value; |
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struct lcd_dma_desc *desc; |
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struct atmel_hlcd_regs *regs; |
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if (!has_lcdc()) |
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return; /* No lcdc */ |
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regs = (struct atmel_hlcd_regs *)panel_info.mmio; |
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/* Disable DISP signal */ |
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); |
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) |
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udelay(1); |
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/* Disable synchronization */ |
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_SYNCDIS); |
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) |
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udelay(1); |
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/* Disable pixel clock */ |
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_CLKDIS); |
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) |
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udelay(1); |
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/* Disable PWM */ |
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lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_PWMDIS); |
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while ((lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) |
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udelay(1); |
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/* Set pixel clock */ |
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value = get_lcdc_clk_rate(0) / panel_info.vl_clk; |
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if (get_lcdc_clk_rate(0) % panel_info.vl_clk) |
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value++; |
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if (value < 1) { |
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/* Using system clock as pixel clock */ |
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lcdc_writel(®s->lcdc_lcdcfg0, |
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LCDC_LCDCFG0_CLKDIV(0) |
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| LCDC_LCDCFG0_CGDISHCR |
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| LCDC_LCDCFG0_CGDISHEO |
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| LCDC_LCDCFG0_CGDISOVR1 |
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| LCDC_LCDCFG0_CGDISBASE |
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| panel_info.vl_clk_pol |
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| LCDC_LCDCFG0_CLKSEL); |
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} else { |
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lcdc_writel(®s->lcdc_lcdcfg0, |
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LCDC_LCDCFG0_CLKDIV(value - 2) |
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| LCDC_LCDCFG0_CGDISHCR |
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| LCDC_LCDCFG0_CGDISHEO |
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| LCDC_LCDCFG0_CGDISOVR1 |
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| LCDC_LCDCFG0_CGDISBASE |
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| panel_info.vl_clk_pol); |
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} |
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/* Initialize control register 5 */ |
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value = 0; |
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value |= panel_info.vl_sync; |
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#ifndef LCD_OUTPUT_BPP |
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/* Output is 24bpp */ |
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value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; |
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#else |
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switch (LCD_OUTPUT_BPP) { |
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case 12: |
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value |= LCDC_LCDCFG5_MODE_OUTPUT_12BPP; |
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break; |
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case 16: |
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value |= LCDC_LCDCFG5_MODE_OUTPUT_16BPP; |
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break; |
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case 18: |
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value |= LCDC_LCDCFG5_MODE_OUTPUT_18BPP; |
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break; |
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case 24: |
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value |= LCDC_LCDCFG5_MODE_OUTPUT_24BPP; |
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break; |
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default: |
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BUG(); |
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break; |
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} |
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#endif |
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value |= LCDC_LCDCFG5_GUARDTIME(ATMEL_LCDC_GUARD_TIME); |
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value |= (LCDC_LCDCFG5_DISPDLY | LCDC_LCDCFG5_VSPDLYS); |
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lcdc_writel(®s->lcdc_lcdcfg5, value); |
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/* Vertical & Horizontal Timing */ |
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value = LCDC_LCDCFG1_VSPW(panel_info.vl_vsync_len - 1); |
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value |= LCDC_LCDCFG1_HSPW(panel_info.vl_hsync_len - 1); |
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lcdc_writel(®s->lcdc_lcdcfg1, value); |
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value = LCDC_LCDCFG2_VBPW(panel_info.vl_lower_margin); |
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value |= LCDC_LCDCFG2_VFPW(panel_info.vl_upper_margin - 1); |
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lcdc_writel(®s->lcdc_lcdcfg2, value); |
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value = LCDC_LCDCFG3_HBPW(panel_info.vl_right_margin - 1); |
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value |= LCDC_LCDCFG3_HFPW(panel_info.vl_left_margin - 1); |
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lcdc_writel(®s->lcdc_lcdcfg3, value); |
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/* Display size */ |
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value = LCDC_LCDCFG4_RPF(panel_info.vl_row - 1); |
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value |= LCDC_LCDCFG4_PPL(panel_info.vl_col - 1); |
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lcdc_writel(®s->lcdc_lcdcfg4, value); |
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lcdc_writel(®s->lcdc_basecfg0, |
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LCDC_BASECFG0_BLEN_AHB_INCR4 | LCDC_BASECFG0_DLBO); |
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switch (NBITS(panel_info.vl_bpix)) { |
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case 16: |
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lcdc_writel(®s->lcdc_basecfg1, |
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LCDC_BASECFG1_RGBMODE_16BPP_RGB_565); |
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break; |
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default: |
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BUG(); |
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break; |
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} |
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lcdc_writel(®s->lcdc_basecfg2, LCDC_BASECFG2_XSTRIDE(0)); |
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lcdc_writel(®s->lcdc_basecfg3, 0); |
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lcdc_writel(®s->lcdc_basecfg4, LCDC_BASECFG4_DMA); |
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/* Disable all interrupts */ |
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lcdc_writel(®s->lcdc_lcdidr, ~0UL); |
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lcdc_writel(®s->lcdc_baseidr, ~0UL); |
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/* Setup the DMA descriptor, this descriptor will loop to itself */ |
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desc = (struct lcd_dma_desc *)(lcdbase - 16); |
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desc->address = (u32)lcdbase; |
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/* Disable DMA transfer interrupt & descriptor loaded interrupt. */ |
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desc->control = LCDC_BASECTRL_ADDIEN | LCDC_BASECTRL_DSCRIEN |
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| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH; |
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desc->next = (u32)desc; |
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lcdc_writel(®s->lcdc_baseaddr, desc->address); |
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lcdc_writel(®s->lcdc_basectrl, desc->control); |
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lcdc_writel(®s->lcdc_basenext, desc->next); |
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lcdc_writel(®s->lcdc_basecher, LCDC_BASECHER_CHEN | |
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LCDC_BASECHER_UPDATEEN); |
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/* Enable LCD */ |
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value = lcdc_readl(®s->lcdc_lcden); |
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_CLKEN); |
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_CLKSTS)) |
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udelay(1); |
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value = lcdc_readl(®s->lcdc_lcden); |
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_SYNCEN); |
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_LCDSTS)) |
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udelay(1); |
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value = lcdc_readl(®s->lcdc_lcden); |
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_DISPEN); |
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_DISPSTS)) |
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udelay(1); |
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value = lcdc_readl(®s->lcdc_lcden); |
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lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN); |
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while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS)) |
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udelay(1); |
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} |
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@ -0,0 +1,231 @@ |
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/*
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* Header file for AT91/AT32 MULTI LAYER LCD Controller |
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* |
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* Data structure and register user interface |
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* |
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* Copyright (C) 2012 Atmel Corporation |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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*/ |
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#ifndef __ATMEL_HLCDC_H__ |
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#define __ATMEL_HLCDC_H__ |
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/* Atmel multi layer lcdc hardware registers */ |
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struct atmel_hlcd_regs { |
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u32 lcdc_lcdcfg0; |
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u32 lcdc_lcdcfg1; |
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u32 lcdc_lcdcfg2; |
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u32 lcdc_lcdcfg3; |
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u32 lcdc_lcdcfg4; |
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u32 lcdc_lcdcfg5; |
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u32 lcdc_lcdcfg6; |
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u32 res1; |
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u32 lcdc_lcden; |
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u32 lcdc_lcddis; |
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u32 lcdc_lcdsr; |
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u32 res2; |
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u32 lcdc_lcdidr; |
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u32 res3[3]; |
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u32 lcdc_basecher; |
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u32 res4[3]; |
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u32 lcdc_baseidr; |
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u32 res5[3]; |
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u32 lcdc_baseaddr; |
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u32 lcdc_basectrl; |
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u32 lcdc_basenext; |
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u32 lcdc_basecfg0; |
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u32 lcdc_basecfg1; |
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u32 lcdc_basecfg2; |
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u32 lcdc_basecfg3; |
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u32 lcdc_basecfg4; |
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}; |
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#define LCDC_LCDCFG0_CLKPOL (0x1 << 0) |
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#define LCDC_LCDCFG0_CLKSEL (0x1 << 2) |
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#define LCDC_LCDCFG0_CLKPWMSEL (0x1 << 3) |
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#define LCDC_LCDCFG0_CGDISBASE (0x1 << 8) |
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#define LCDC_LCDCFG0_CGDISOVR1 (0x1 << 9) |
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#define LCDC_LCDCFG0_CGDISHEO (0x1 << 11) |
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#define LCDC_LCDCFG0_CGDISHCR (0x1 << 12) |
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#define LCDC_LCDCFG0_CLKDIV_Pos 16 |
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#define LCDC_LCDCFG0_CLKDIV_Msk (0xff << LCDC_LCDCFG0_CLKDIV_Pos) |
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#define LCDC_LCDCFG0_CLKDIV(value) \ |
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((LCDC_LCDCFG0_CLKDIV_Msk & ((value) << LCDC_LCDCFG0_CLKDIV_Pos))) |
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#define LCDC_LCDCFG1_HSPW_Pos 0 |
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#define LCDC_LCDCFG1_HSPW_Msk (0x3f << LCDC_LCDCFG1_HSPW_Pos) |
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#define LCDC_LCDCFG1_HSPW(value) \ |
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((LCDC_LCDCFG1_HSPW_Msk & ((value) << LCDC_LCDCFG1_HSPW_Pos))) |
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#define LCDC_LCDCFG1_VSPW_Pos 16 |
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#define LCDC_LCDCFG1_VSPW_Msk (0x3f << LCDC_LCDCFG1_VSPW_Pos) |
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#define LCDC_LCDCFG1_VSPW(value) \ |
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((LCDC_LCDCFG1_VSPW_Msk & ((value) << LCDC_LCDCFG1_VSPW_Pos))) |
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#define LCDC_LCDCFG2_VFPW_Pos 0 |
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#define LCDC_LCDCFG2_VFPW_Msk (0x3f << LCDC_LCDCFG2_VFPW_Pos) |
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#define LCDC_LCDCFG2_VFPW(value) \ |
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((LCDC_LCDCFG2_VFPW_Msk & ((value) << LCDC_LCDCFG2_VFPW_Pos))) |
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#define LCDC_LCDCFG2_VBPW_Pos 16 |
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#define LCDC_LCDCFG2_VBPW_Msk (0x3f << LCDC_LCDCFG2_VBPW_Pos) |
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#define LCDC_LCDCFG2_VBPW(value) \ |
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((LCDC_LCDCFG2_VBPW_Msk & ((value) << LCDC_LCDCFG2_VBPW_Pos))) |
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#define LCDC_LCDCFG3_HFPW_Pos 0 |
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#define LCDC_LCDCFG3_HFPW_Msk (0xff << LCDC_LCDCFG3_HFPW_Pos) |
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#define LCDC_LCDCFG3_HFPW(value) \ |
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((LCDC_LCDCFG3_HFPW_Msk & ((value) << LCDC_LCDCFG3_HFPW_Pos))) |
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#define LCDC_LCDCFG3_HBPW_Pos 16 |
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#define LCDC_LCDCFG3_HBPW_Msk (0xff << LCDC_LCDCFG3_HBPW_Pos) |
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#define LCDC_LCDCFG3_HBPW(value) \ |
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((LCDC_LCDCFG3_HBPW_Msk & ((value) << LCDC_LCDCFG3_HBPW_Pos))) |
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#define LCDC_LCDCFG4_PPL_Pos 0 |
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#define LCDC_LCDCFG4_PPL_Msk (0x7ff << LCDC_LCDCFG4_PPL_Pos) |
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#define LCDC_LCDCFG4_PPL(value) \ |
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((LCDC_LCDCFG4_PPL_Msk & ((value) << LCDC_LCDCFG4_PPL_Pos))) |
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#define LCDC_LCDCFG4_RPF_Pos 16 |
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#define LCDC_LCDCFG4_RPF_Msk (0x7ff << LCDC_LCDCFG4_RPF_Pos) |
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#define LCDC_LCDCFG4_RPF(value) \ |
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((LCDC_LCDCFG4_RPF_Msk & ((value) << LCDC_LCDCFG4_RPF_Pos))) |
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|
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#define LCDC_LCDCFG5_HSPOL (0x1 << 0) |
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#define LCDC_LCDCFG5_VSPOL (0x1 << 1) |
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#define LCDC_LCDCFG5_VSPDLYS (0x1 << 2) |
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#define LCDC_LCDCFG5_VSPDLYE (0x1 << 3) |
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#define LCDC_LCDCFG5_DISPPOL (0x1 << 4) |
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#define LCDC_LCDCFG5_SERIAL (0x1 << 5) |
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#define LCDC_LCDCFG5_DITHER (0x1 << 6) |
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#define LCDC_LCDCFG5_DISPDLY (0x1 << 7) |
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#define LCDC_LCDCFG5_MODE_Pos 8 |
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#define LCDC_LCDCFG5_MODE_Msk (0x3 << LCDC_LCDCFG5_MODE_Pos) |
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#define LCDC_LCDCFG5_MODE_OUTPUT_12BPP (0x0 << 8) |
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#define LCDC_LCDCFG5_MODE_OUTPUT_16BPP (0x1 << 8) |
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#define LCDC_LCDCFG5_MODE_OUTPUT_18BPP (0x2 << 8) |
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#define LCDC_LCDCFG5_MODE_OUTPUT_24BPP (0x3 << 8) |
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#define LCDC_LCDCFG5_VSPSU (0x1 << 12) |
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#define LCDC_LCDCFG5_VSPHO (0x1 << 13) |
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#define LCDC_LCDCFG5_GUARDTIME_Pos 16 |
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#define LCDC_LCDCFG5_GUARDTIME_Msk (0x1f << LCDC_LCDCFG5_GUARDTIME_Pos) |
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#define LCDC_LCDCFG5_GUARDTIME(value) \ |
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((LCDC_LCDCFG5_GUARDTIME_Msk & ((value) << LCDC_LCDCFG5_GUARDTIME_Pos))) |
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|
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#define LCDC_LCDCFG6_PWMPS_Pos 0 |
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#define LCDC_LCDCFG6_PWMPS_Msk (0x7 << LCDC_LCDCFG6_PWMPS_Pos) |
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#define LCDC_LCDCFG6_PWMPS(value) \ |
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((LCDC_LCDCFG6_PWMPS_Msk & ((value) << LCDC_LCDCFG6_PWMPS_Pos))) |
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#define LCDC_LCDCFG6_PWMPOL (0x1 << 4) |
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#define LCDC_LCDCFG6_PWMCVAL_Pos 8 |
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#define LCDC_LCDCFG6_PWMCVAL_Msk (0xff << LCDC_LCDCFG6_PWMCVAL_Pos) |
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#define LCDC_LCDCFG6_PWMCVAL(value) \ |
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((LCDC_LCDCFG6_PWMCVAL_Msk & ((value) << LCDC_LCDCFG6_PWMCVAL_Pos))) |
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|
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#define LCDC_LCDEN_CLKEN (0x1 << 0) |
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#define LCDC_LCDEN_SYNCEN (0x1 << 1) |
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#define LCDC_LCDEN_DISPEN (0x1 << 2) |
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#define LCDC_LCDEN_PWMEN (0x1 << 3) |
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|
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#define LCDC_LCDDIS_CLKDIS (0x1 << 0) |
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#define LCDC_LCDDIS_SYNCDIS (0x1 << 1) |
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#define LCDC_LCDDIS_DISPDIS (0x1 << 2) |
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#define LCDC_LCDDIS_PWMDIS (0x1 << 3) |
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#define LCDC_LCDDIS_CLKRST (0x1 << 8) |
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#define LCDC_LCDDIS_SYNCRST (0x1 << 9) |
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#define LCDC_LCDDIS_DISPRST (0x1 << 10) |
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#define LCDC_LCDDIS_PWMRST (0x1 << 11) |
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|
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#define LCDC_LCDSR_CLKSTS (0x1 << 0) |
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#define LCDC_LCDSR_LCDSTS (0x1 << 1) |
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#define LCDC_LCDSR_DISPSTS (0x1 << 2) |
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#define LCDC_LCDSR_PWMSTS (0x1 << 3) |
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#define LCDC_LCDSR_SIPSTS (0x1 << 4) |
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|
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#define LCDC_LCDIDR_SOFID (0x1 << 0) |
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#define LCDC_LCDIDR_DISID (0x1 << 1) |
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#define LCDC_LCDIDR_DISPID (0x1 << 2) |
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#define LCDC_LCDIDR_FIFOERRID (0x1 << 4) |
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#define LCDC_LCDIDR_BASEID (0x1 << 8) |
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#define LCDC_LCDIDR_OVR1ID (0x1 << 9) |
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#define LCDC_LCDIDR_HEOID (0x1 << 11) |
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#define LCDC_LCDIDR_HCRID (0x1 << 12) |
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|
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#define LCDC_BASECHER_CHEN (0x1 << 0) |
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#define LCDC_BASECHER_UPDATEEN (0x1 << 1) |
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#define LCDC_BASECHER_A2QEN (0x1 << 2) |
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|
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#define LCDC_BASEIDR_DMA (0x1 << 2) |
||||
#define LCDC_BASEIDR_DSCR (0x1 << 3) |
||||
#define LCDC_BASEIDR_ADD (0x1 << 4) |
||||
#define LCDC_BASEIDR_DONE (0x1 << 5) |
||||
#define LCDC_BASEIDR_OVR (0x1 << 6) |
||||
|
||||
#define LCDC_BASECTRL_DFETCH (0x1 << 0) |
||||
#define LCDC_BASECTRL_LFETCH (0x1 << 1) |
||||
#define LCDC_BASECTRL_DMAIEN (0x1 << 2) |
||||
#define LCDC_BASECTRL_DSCRIEN (0x1 << 3) |
||||
#define LCDC_BASECTRL_ADDIEN (0x1 << 4) |
||||
#define LCDC_BASECTRL_DONEIEN (0x1 << 5) |
||||
|
||||
#define LCDC_BASECFG0_BLEN_Pos 4 |
||||
#define LCDC_BASECFG0_BLEN_AHB_SINGLE (0x0 << 4) |
||||
#define LCDC_BASECFG0_BLEN_AHB_INCR4 (0x1 << 4) |
||||
#define LCDC_BASECFG0_BLEN_AHB_INCR8 (0x2 << 4) |
||||
#define LCDC_BASECFG0_BLEN_AHB_INCR16 (0x3 << 4) |
||||
#define LCDC_BASECFG0_DLBO (0x1 << 8) |
||||
|
||||
#define LCDC_BASECFG1_RGBMODE_12BPP_RGB_444 (0x0 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_ARGB_4444 (0x1 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_RGBA_4444 (0x2 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_RGB_565 (0x3 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_16BPP_TRGB_1555 (0x4 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666 (0x5 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_18BPP_RGB_666_PACKED (0x6 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_1666 (0x7 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_19BPP_TRGB_PACKED (0x8 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888 (0x9 << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_24BPP_RGB_888_PACKED (0xA << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_25BPP_TRGB_1888 (0xB << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_32BPP_ARGB_8888 (0xC << 4) |
||||
#define LCDC_BASECFG1_RGBMODE_32BPP_RGBA_8888 (0xD << 4) |
||||
|
||||
#define LCDC_BASECFG2_XSTRIDE_Pos 0 |
||||
#define LCDC_BASECFG2_XSTRIDE_Msk (0xffffffff << LCDC_BASECFG2_XSTRIDE_Pos) |
||||
#define LCDC_BASECFG2_XSTRIDE(value) \ |
||||
((LCDC_BASECFG2_XSTRIDE_Msk & ((value) << LCDC_BASECFG2_XSTRIDE_Pos))) |
||||
|
||||
#define LCDC_BASECFG3_BDEF_Pos 0 |
||||
#define LCDC_BASECFG3_BDEF_Msk (0xff << LCDC_BASECFG3_BDEF_Pos) |
||||
#define LCDC_BASECFG3_BDEF(value) \ |
||||
((LCDC_BASECFG3_BDEF_Msk & ((value) << LCDC_BASECFG3_BDEF_Pos))) |
||||
#define LCDC_BASECFG3_GDEF_Pos 8 |
||||
#define LCDC_BASECFG3_GDEF_Msk (0xff << LCDC_BASECFG3_GDEF_Pos) |
||||
#define LCDC_BASECFG3_GDEF(value) \ |
||||
((LCDC_BASECFG3_GDEF_Msk & ((value) << LCDC_BASECFG3_GDEF_Pos))) |
||||
#define LCDC_BASECFG3_RDEF_Pos 16 |
||||
#define LCDC_BASECFG3_RDEF_Msk (0xff << LCDC_BASECFG3_RDEF_Pos) |
||||
#define LCDC_BASECFG3_RDEF(value) \ |
||||
((LCDC_BASECFG3_RDEF_Msk & ((value) << LCDC_BASECFG3_RDEF_Pos))) |
||||
|
||||
#define LCDC_BASECFG4_DMA (0x1 << 8) |
||||
#define LCDC_BASECFG4_REP (0x1 << 9) |
||||
|
||||
struct lcd_dma_desc { |
||||
u32 address; |
||||
u32 control; |
||||
u32 next; |
||||
}; |
||||
|
||||
#define ATMEL_LCDC_LUT(n) (0x0400 + ((n)*4)) |
||||
|
||||
#endif /* __ATMEL_HLCDC_H__ */ |
||||
@ -0,0 +1,29 @@ |
||||
/*
|
||||
* (C) Copyright 2012 Samsung Electronics |
||||
* Donghwa Lee <dh09.lee@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* aint with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _LIBTIZEN_H_ |
||||
#define _LIBTIZEN_H_ |
||||
|
||||
#define HD_RESOLUTION 0 |
||||
|
||||
void get_tizen_logo_info(vidinfo_t *vid); |
||||
|
||||
#endif /* _LIBTIZEN_H_ */ |
||||
@ -0,0 +1,46 @@ |
||||
#
|
||||
# (C) Copyright 2012 Samsung Electronics
|
||||
# Donghwa Lee <dh09.lee@samsung.com>
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
include $(TOPDIR)/config.mk |
||||
|
||||
LIB = $(obj)libtizen.o
|
||||
|
||||
SOBJS =
|
||||
|
||||
COBJS-$(CONFIG_TIZEN) += tizen.o
|
||||
|
||||
COBJS := $(sort $(COBJS-y))
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
|
||||
$(LIB): $(obj).depend $(OBJS) |
||||
$(call cmd_link_o_target, $(OBJS))
|
||||
|
||||
#########################################################################
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk |
||||
|
||||
sinclude $(obj).depend |
||||
|
||||
#########################################################################
|
||||
@ -0,0 +1,40 @@ |
||||
/*
|
||||
* (C) Copyright 2012 Samsung Electronics |
||||
* Donghwa Lee <dh09.lee@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* aint with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#include <common.h> |
||||
#include <lcd.h> |
||||
#include <libtizen.h> |
||||
|
||||
#include "tizen_hd_logo.h" |
||||
#include "tizen_hd_logo_data.h" |
||||
|
||||
void get_tizen_logo_info(vidinfo_t *vid) |
||||
{ |
||||
switch (vid->resolution) { |
||||
case HD_RESOLUTION: |
||||
vid->logo_width = TIZEN_HD_LOGO_WIDTH; |
||||
vid->logo_height = TIZEN_HD_LOGO_HEIGHT; |
||||
vid->logo_addr = (ulong)tizen_hd_logo; |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
} |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,29 @@ |
||||
/*
|
||||
* (C) Copyright 2012 Samsung Electronics |
||||
* Donghwa Lee <dh09.lee@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation; either version 2 of |
||||
* the License, or (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* aint with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
||||
* MA 02111-1307 USA |
||||
* |
||||
*/ |
||||
|
||||
#ifndef _TIZEN_HD_LOGO_DATA_H_ |
||||
#define _TIZEN_HD_LOGO_DATA_H_ |
||||
|
||||
#define TIZEN_HD_LOGO_WIDTH 520 |
||||
#define TIZEN_HD_LOGO_HEIGHT 120 |
||||
#define TIZEN_HD_LOGO_BPP 32 |
||||
|
||||
#endif /* _TIZEN_HD_LOGO_DATA_H_ */ |
||||
Loading…
Reference in new issue