This adds the Gumstix DuoVero machine [1]. This is a OMAP4430-based computer-on-module (COM aka SOM) that can be mounted on various expansion boards with different peripherals. [1] https://store.gumstix.com/index.php/category/43/ Signed-off-by: Ash Charles <ash@gumstix.com> [trini: Rename gpmc_enable_gpmc_cs_config to gpmc_enable_gpmc_net_config] Signed-off-by: Tom Rini <trini@ti.com>master
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := duovero.o
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/*
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* (C) Copyright 2013 |
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* Gumstix Inc. <www.gumstix.com> |
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* Maintainer: Ash Charles <ash@gumstix.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <common.h> |
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#include <netdev.h> |
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#include <asm/arch/sys_proto.h> |
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#include <asm/arch/mmc_host_def.h> |
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#include <twl6030.h> |
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#include <asm/emif.h> |
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#include <asm/arch/clock.h> |
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#include <asm/arch/gpio.h> |
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#include <asm/gpio.h> |
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#include "duovero_mux_data.h" |
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#define WIFI_EN 43 |
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#if defined(CONFIG_CMD_NET) |
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#define SMSC_NRESET 45 |
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static void setup_net_chip(void); |
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#endif |
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#ifdef CONFIG_USB_EHCI |
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#include <usb.h> |
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#include <asm/arch/ehci.h> |
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#include <asm/ehci-omap.h> |
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#endif |
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DECLARE_GLOBAL_DATA_PTR; |
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const struct omap_sysinfo sysinfo = { |
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"Board: duovero\n" |
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}; |
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struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000; |
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/**
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* @brief board_init |
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* |
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* @return 0 |
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*/ |
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int board_init(void) |
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{ |
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gpmc_init(); |
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gd->bd->bi_arch_number = MACH_TYPE_OMAP4_DUOVERO; |
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; |
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return 0; |
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} |
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/**
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* @brief misc_init_r - Configure board specific configurations |
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* such as power configurations, ethernet initialization as phase2 of |
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* boot sequence |
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* |
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* @return 0 |
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*/ |
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int misc_init_r(void) |
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{ |
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int ret = 0; |
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u8 val; |
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/* wifi setup: first enable 32Khz clock from 6030 pmic */ |
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val = 0xe1; |
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ret = i2c_write(TWL6030_CHIP_PM, 0xbe, 1, &val, 1); |
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if (ret) |
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printf("Failed to enable 32Khz clock to wifi module\n"); |
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/* then setup WIFI_EN as an output pin and send reset pulse */ |
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if (!gpio_request(WIFI_EN, "")) { |
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gpio_direction_output(WIFI_EN, 0); |
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gpio_set_value(WIFI_EN, 1); |
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udelay(1); |
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gpio_set_value(WIFI_EN, 0); |
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udelay(1); |
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gpio_set_value(WIFI_EN, 1); |
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} |
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#if defined(CONFIG_CMD_NET) |
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setup_net_chip(); |
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#endif |
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return 0; |
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} |
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void set_muxconf_regs_essential(void) |
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{ |
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do_set_mux((*ctrl)->control_padconf_core_base, |
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core_padconf_array_essential, |
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sizeof(core_padconf_array_essential) / |
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sizeof(struct pad_conf_entry)); |
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do_set_mux((*ctrl)->control_padconf_wkup_base, |
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wkup_padconf_array_essential, |
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sizeof(wkup_padconf_array_essential) / |
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sizeof(struct pad_conf_entry)); |
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do_set_mux((*ctrl)->control_padconf_core_base, |
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core_padconf_array_non_essential, |
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sizeof(core_padconf_array_non_essential) / |
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sizeof(struct pad_conf_entry)); |
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do_set_mux((*ctrl)->control_padconf_wkup_base, |
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wkup_padconf_array_non_essential, |
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sizeof(wkup_padconf_array_non_essential) / |
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sizeof(struct pad_conf_entry)); |
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} |
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC) |
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int board_mmc_init(bd_t *bis) |
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{ |
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return omap_mmc_init(0, 0, 0, -1, -1); |
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} |
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#endif |
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#if defined(CONFIG_CMD_NET) |
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#define GPMC_SIZE_16M 0xF |
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#define GPMC_BASEADDR_MASK 0x3F |
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#define GPMC_CS_ENABLE 0x1 |
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static void enable_gpmc_net_config(const u32 *gpmc_config, struct gpmc_cs *cs, |
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u32 base, u32 size) |
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{ |
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writel(0, &cs->config7); |
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sdelay(1000); |
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/* Delay for settling */ |
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writel(gpmc_config[0], &cs->config1); |
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writel(gpmc_config[1], &cs->config2); |
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writel(gpmc_config[2], &cs->config3); |
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writel(gpmc_config[3], &cs->config4); |
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writel(gpmc_config[4], &cs->config5); |
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writel(gpmc_config[5], &cs->config6); |
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/*
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* Enable the config. size is the CS size and goes in |
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* bits 11:8. We set bit 6 to enable this CS and the base |
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* address goes into bits 5:0. |
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*/ |
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writel((size << 8) | (GPMC_CS_ENABLE << 6) | |
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((base >> 24) & GPMC_BASEADDR_MASK), |
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&cs->config7); |
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sdelay(2000); |
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} |
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/* GPMC CS configuration for an SMSC LAN9221 ethernet controller */ |
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#define NET_LAN9221_GPMC_CONFIG1 0x2a001203 |
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#define NET_LAN9221_GPMC_CONFIG2 0x000a0a02 |
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#define NET_LAN9221_GPMC_CONFIG3 0x00020200 |
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#define NET_LAN9221_GPMC_CONFIG4 0x0a030a03 |
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#define NET_LAN9221_GPMC_CONFIG5 0x000a0a0a |
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#define NET_LAN9221_GPMC_CONFIG6 0x8a070707 |
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#define NET_LAN9221_GPMC_CONFIG7 0x00000f6c |
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/* GPMC definitions for LAN9221 chips on expansion boards */ |
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static const u32 gpmc_lan_config[] = { |
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NET_LAN9221_GPMC_CONFIG1, |
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NET_LAN9221_GPMC_CONFIG2, |
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NET_LAN9221_GPMC_CONFIG3, |
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NET_LAN9221_GPMC_CONFIG4, |
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NET_LAN9221_GPMC_CONFIG5, |
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NET_LAN9221_GPMC_CONFIG6, |
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/*CONFIG7- computed as params */ |
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}; |
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/*
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* Routine: setup_net_chip |
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* Description: Setting up the configuration GPMC registers specific to the |
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* Ethernet hardware. |
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*/ |
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static void setup_net_chip(void) |
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{ |
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enable_gpmc_net_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000, |
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GPMC_SIZE_16M); |
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/* Make GPIO SMSC_NRESET as output pin and send reset pulse */ |
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if (!gpio_request(SMSC_NRESET, "")) { |
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gpio_direction_output(SMSC_NRESET, 0); |
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gpio_set_value(SMSC_NRESET, 1); |
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udelay(1); |
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gpio_set_value(SMSC_NRESET, 0); |
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udelay(1); |
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gpio_set_value(SMSC_NRESET, 1); |
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} |
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} |
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#endif |
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int board_eth_init(bd_t *bis) |
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{ |
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int rc = 0; |
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#ifdef CONFIG_SMC911X |
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
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#endif |
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return rc; |
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} |
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#ifdef CONFIG_USB_EHCI |
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static struct omap_usbhs_board_data usbhs_bdata = { |
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, |
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.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED, |
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, |
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}; |
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int ehci_hcd_init(int index, enum usb_init_type init, |
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struct ehci_hccr **hccr, struct ehci_hcor **hcor) |
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{ |
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int ret; |
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unsigned int utmi_clk; |
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u32 auxclk, altclksrc; |
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/* Now we can enable our port clocks */ |
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utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL); |
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utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK; |
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setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk); |
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auxclk = readl(&scrm->auxclk3); |
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/* Select sys_clk */ |
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auxclk &= ~AUXCLK_SRCSELECT_MASK; |
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auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT; |
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/* Set the divisor to 2 */ |
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auxclk &= ~AUXCLK_CLKDIV_MASK; |
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auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT; |
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/* Request auxilary clock #3 */ |
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auxclk |= AUXCLK_ENABLE_MASK; |
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writel(auxclk, &scrm->auxclk3); |
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altclksrc = readl(&scrm->altclksrc); |
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/* Activate alternate system clock supplier */ |
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altclksrc &= ~ALTCLKSRC_MODE_MASK; |
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altclksrc |= ALTCLKSRC_MODE_ACTIVE; |
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/* enable clocks */ |
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altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK; |
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writel(altclksrc, &scrm->altclksrc); |
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ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor); |
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if (ret < 0) |
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return ret; |
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return 0; |
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} |
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int ehci_hcd_stop(int index) |
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{ |
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return omap_ehci_hcd_stop(); |
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} |
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#endif |
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/*
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* get_board_rev() - get board revision |
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*/ |
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u32 get_board_rev(void) |
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{ |
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return 0x20; |
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} |
@ -0,0 +1,199 @@ |
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/*
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* (C) Copyright 2012 |
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* Gumstix Incorporated, <www.gumstix.com> |
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* Maintainer: Ash Charles <ash@gumstix.com> |
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* |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#ifndef _DUOVERO_MUX_DATA_H_ |
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#define _DUOVERO_MUX_DATA_H_ |
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#include <asm/arch/mux_omap4.h> |
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const struct pad_conf_entry core_padconf_array_essential[] = { |
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{SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ |
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{SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ |
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{SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ |
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{SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ |
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{SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ |
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{SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ |
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{I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ |
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{I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ |
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{I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ |
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{I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ |
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{I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ |
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{I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ |
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{I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ |
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{I2C4_SDA, (PTU | IEN | M0)}, /* i2c4_sda */ |
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{UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ |
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{UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ |
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{UART3_RX_IRRX, (PTU | IEN | M0)}, /* uart3_rx */ |
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{UART3_TX_IRTX, (M0)} /* uart3_tx */ |
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}; |
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const struct pad_conf_entry wkup_padconf_array_essential[] = { |
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{PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ |
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{PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ |
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{PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ |
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}; |
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const struct pad_conf_entry core_padconf_array_non_essential[] = { |
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{GPMC_AD0, (PTU | IEN | M0)}, /* gpmc_ad0 */ |
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{GPMC_AD1, (PTU | IEN | M0)}, /* gpmc_ad1 */ |
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{GPMC_AD2, (PTU | IEN | M0)}, /* gpmc_ad2 */ |
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{GPMC_AD3, (PTU | IEN | M0)}, /* gpmc_ad3 */ |
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{GPMC_AD4, (PTU | IEN | M0)}, /* gpmc_ad4 */ |
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{GPMC_AD5, (PTU | IEN | M0)}, /* gpmc_ad5 */ |
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{GPMC_AD6, (PTU | IEN | M0)}, /* gpmc_ad6 */ |
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{GPMC_AD7, (PTU | IEN | M0)}, /* gpmc_ad7 */ |
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{GPMC_AD8, (PTU | IEN | M0)}, /* gpmc_ad8 */ |
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{GPMC_AD9, (PTU | IEN | M0)}, /* gpmc_ad9 */ |
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{GPMC_AD10, (PTU | IEN | M0)}, /* gpmc_ad10 */ |
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{GPMC_AD11, (PTU | IEN | M0)}, /* gpmc_ad11 */ |
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{GPMC_AD12, (PTU | IEN | M0)}, /* gpmc_ad12 */ |
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{GPMC_AD13, (PTU | IEN | M0)}, /* gpmc_ad13 */ |
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{GPMC_AD14, (PTU | IEN | M0)}, /* gpmc_ad14 */ |
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{GPMC_AD15, (PTU | IEN | M0)}, /* gpmc_ad15 */ |
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{GPMC_A16, (PTU | IEN | M3)}, /* gpio_40 */ |
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{GPMC_A17, (PTU | IEN | M3)}, /* gpio_41 - hdmi_ls_oe */ |
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{GPMC_A18, (PTU | IEN | M3)}, /* gpio_42 */ |
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{GPMC_A19, (PTU | IEN | M3)}, /* gpio_43 - wifi_en */ |
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{GPMC_A20, (PTU | IEN | M3)}, /* gpio_44 - eth_irq */ |
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{GPMC_A21, (PTU | IEN | M3)}, /* gpio_45 - eth_nreset */ |
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{GPMC_A22, (PTU | IEN | M3)}, /* gpio_46 - eth_pme */ |
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{GPMC_A23, (PTU | IEN | M3)}, /* gpio_47 */ |
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{GPMC_A24, (PTU | IEN | M3)}, /* gpio_48 - eth_mdix */ |
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{GPMC_A25, (PTU | IEN | M3)}, /* gpio_49 - bt_wakeup */ |
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{GPMC_NCS0, (PTU | M0)}, /* gpmc_ncs0 */ |
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{GPMC_NCS1, (PTU | M0)}, /* gpmc_ncs1 */ |
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{GPMC_NCS2, (PTU | M0)}, /* gpmc_ncs2 */ |
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{GPMC_NCS3, (PTU | IEN | M3)}, /* gpio_53 */ |
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{C2C_DATA12, (PTU | M0)}, /* gpmc_ncs4 */ |
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{C2C_DATA13, (PTU | M0)}, /* gpmc_ncs5 - eth_cs */ |
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{GPMC_NWP, (PTU | IEN | M0)}, /* gpmc_nwp */ |
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{GPMC_CLK, (PTU | IEN | M0)}, /* gpmc_clk */ |
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{GPMC_NADV_ALE, (PTU | M0)}, /* gpmc_nadv_ale */ |
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{GPMC_NBE0_CLE, (PTU | M0)}, /* gpmc_nbe0_cle */ |
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{GPMC_NBE1, (PTU | M0)}, /* gpmc_nbe1 */ |
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{GPMC_WAIT0, (PTU | IEN | M0)}, /* gpmc_wait0 */ |
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{GPMC_WAIT1, (PTU | IEN | M0)}, /* gpio_62 - usbh_nreset */ |
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{GPMC_NOE, (PTU | M0)}, /* gpmc_noe */ |
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{GPMC_NWE, (PTU | M0)}, /* gpmc_nwe */ |
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{HDMI_HPD, (PTD | IEN | M3)}, /* gpio_63 - hdmi_hpd */ |
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{HDMI_CEC, (PTU | IEN | M0)}, /* hdmi_cec */ |
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{HDMI_DDC_SCL, (M0)}, /* hdmi_ddc_scl */ |
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{HDMI_DDC_SDA, (IEN | M0)}, /* hdmi_ddc_sda */ |
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{CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ |
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{CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ |
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{CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ |
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{CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ |
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{CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ |
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{CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ |
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{CSI21_DX3, (IEN | M0)}, /* csi21_dx3 */ |
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{CSI21_DY3, (IEN | M0)}, /* csi21_dy3 */ |
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{CSI21_DX4, (IEN | M0)}, /* csi21_dx4 */ |
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{CSI21_DY4, (IEN | M0)}, /* csi21_dy4 */ |
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{CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ |
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{CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ |
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{CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ |
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{CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ |
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{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */ |
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{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */ |
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{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */ |
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{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */ |
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{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */ |
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{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */ |
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{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */ |
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{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */ |
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{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ |
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{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ |
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{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ |
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{USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ |
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{USBB1_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_96 - usbh_cpen */ |
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{USBB1_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_97 - usbh_reset */ |
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{ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ |
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{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ |
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{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ |
||||
{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ |
||||
{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ |
||||
{ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ |
||||
{ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ |
||||
{ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ |
||||
{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ |
||||
{ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ |
||||
{ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ |
||||
{ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ |
||||
{ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ |
||||
{UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ |
||||
{UART2_RTS, (M0)}, /* uart2_rts */ |
||||
{UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ |
||||
{UART2_TX, (M0)}, /* uart2_tx */ |
||||
{HDQ_SIO, (M0)}, /* hdq-sio */ |
||||
{MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ |
||||
{MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ |
||||
{MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ |
||||
{MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ |
||||
{MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs1 */ |
||||
{SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_clk */ |
||||
{SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ |
||||
{SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ |
||||
{SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ |
||||
{SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ |
||||
{SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ |
||||
{MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ |
||||
{MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ |
||||
{MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ |
||||
{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ |
||||
{UART4_RX, (IEN | PTU | M0)}, /* uart4_rx */ |
||||
{UART4_TX, (M0)}, /* uart4_tx */ |
||||
{USBB2_ULPITLL_CLK, (PTU | IEN | M3)}, /* gpio_157 - start_adc */ |
||||
{USBB2_ULPITLL_STP, (PTU | IEN | M3)}, /* gpio_158 - spi_nirq */ |
||||
{USBB2_ULPITLL_DIR, (PTU | IEN | M3)}, /* gpio_159 - bt_nreset */ |
||||
{USBB2_ULPITLL_NXT, (PTU | IEN | M3)}, /* gpio_160 - audio_pwron*/ |
||||
{USBB2_ULPITLL_DAT0, (PTU | IEN | M3)}, /* gpio_161 - bid_0 */ |
||||
{USBB2_ULPITLL_DAT1, (PTU | IEN | M3)}, /* gpio_162 - bid_1 */ |
||||
{USBB2_ULPITLL_DAT2, (PTU | IEN | M3)}, /* gpio_163 - bid_2 */ |
||||
{USBB2_ULPITLL_DAT3, (PTU | IEN | M3)}, /* gpio_164 - bid_3 */ |
||||
{USBB2_ULPITLL_DAT4, (PTU | IEN | M3)}, /* gpio_165 - bid_4 */ |
||||
{USBB2_ULPITLL_DAT5, (PTU | IEN | M3)}, /* gpio_166 - ts_irq*/ |
||||
{USBB2_ULPITLL_DAT6, (PTU | IEN | M3)}, /* gpio_167 - gps_pps */ |
||||
{USBB2_ULPITLL_DAT7, (PTU | IEN | M3)}, /* gpio_168 */ |
||||
{USBB2_HSIC_DATA, (PTU | IEN | M3)}, /* gpio_169 */ |
||||
{USBB2_HSIC_STROBE, (PTU | IEN | M3)}, /* gpio_170 */ |
||||
{UNIPRO_TX1, (PTU | IEN | M3)}, /* gpio_173 */ |
||||
{USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ |
||||
{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ |
||||
{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ |
||||
{SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ |
||||
{SYS_NIRQ2, (PTU | IEN | M0)}, /* sys_nirq2 */ |
||||
{SYS_BOOT0, (M0)}, /* sys_boot0 */ |
||||
{SYS_BOOT1, (M0)}, /* sys_boot1 */ |
||||
{SYS_BOOT2, (M0)}, /* sys_boot2 */ |
||||
{SYS_BOOT3, (M0)}, /* sys_boot3 */ |
||||
{SYS_BOOT4, (M0)}, /* sys_boot4 */ |
||||
{SYS_BOOT5, (M0)}, /* sys_boot5 */ |
||||
{DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ |
||||
{DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ |
||||
{DPM_EMU16, (PTU | IEN | M3)}, /* gpio_27 */ |
||||
{DPM_EMU17, (PTU | IEN | M3)}, /* gpio_28 */ |
||||
{DPM_EMU18, (PTU | IEN | M3)}, /* gpio_29 */ |
||||
{DPM_EMU19, (PTU | IEN | M3)}, /* gpio_30 */ |
||||
}; |
||||
|
||||
const struct pad_conf_entry wkup_padconf_array_non_essential[] = { |
||||
{PAD1_FREF_XTAL_IN, (M0)}, /* fref_xtal_in */ |
||||
{PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ |
||||
{PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ |
||||
{PAD0_FREF_CLK0_OUT, (M7)}, /* safe mode */ |
||||
{PAD1_FREF_CLK3_REQ, M7}, /* safe mode */ |
||||
{PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ |
||||
{PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ |
||||
{PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ |
||||
{PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ |
||||
{PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ |
||||
{PAD0_SYS_BOOT6, (M0)}, /* sys_boot6 */ |
||||
{PAD1_SYS_BOOT7, (M0)}, /* sys_boot7 */ |
||||
}; |
||||
|
||||
|
||||
#endif /* _DUOVERO_MUX_DATA_H_ */ |
@ -0,0 +1,62 @@ |
||||
/*
|
||||
* (C) Copyright: 2013 |
||||
* Gumstix, Inc - http://www.gumstix.com
|
||||
* Maintainer: Ash Charles <ash@gumstix.com> |
||||
* |
||||
* Configuration settings for the Gumstix DuoVero board. |
||||
* See omap4_common.h for OMAP4 common part |
||||
* |
||||
* SPDX-License-Identifier: GPL-2.0+ |
||||
*/ |
||||
|
||||
#ifndef __CONFIG_DUOVERO_H |
||||
#define __CONFIG_DUOVERO_H |
||||
|
||||
/*
|
||||
* High Level Configuration Options |
||||
*/ |
||||
#define CONFIG_DUOVERO |
||||
#define MACH_TYPE_OMAP4_DUOVERO 4097 /* Until the next sync */ |
||||
#define CONFIG_MACH_TYPE MACH_TYPE_OMAP4_DUOVERO |
||||
|
||||
#include <configs/ti_omap4_common.h> |
||||
|
||||
#undef CONFIG_SPL_OS_BOOT |
||||
|
||||
#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
||||
#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION |
||||
#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS |
||||
|
||||
#undef CONFIG_SYS_PROMPT |
||||
#define CONFIG_SYS_PROMPT "duovero # " |
||||
|
||||
/* USB UHH support options */ |
||||
#define CONFIG_CMD_USB |
||||
#define CONFIG_USB_HOST |
||||
#define CONFIG_USB_EHCI |
||||
#define CONFIG_USB_EHCI_OMAP |
||||
#define CONFIG_USB_STORAGE |
||||
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 |
||||
|
||||
#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 |
||||
#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 |
||||
|
||||
#define CONFIG_SYS_ENABLE_PADS_ALL |
||||
|
||||
#define CONFIG_CMD_PING |
||||
#define CONFIG_CMD_DHCP |
||||
#define CONFIG_CMD_NET |
||||
|
||||
#define CONFIG_SMC911X |
||||
#define CONFIG_SMC911X_32_BIT |
||||
#define CONFIG_SMC911X_BASE 0x2C000000 |
||||
|
||||
/* GPIO */ |
||||
#define CONFIG_CMD_GPIO |
||||
|
||||
/* ENV related config options */ |
||||
#define CONFIG_ENV_IS_NOWHERE |
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
||||
|
||||
#endif /* __CONFIG_DUOVERO_H */ |
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Reference in new issue