Add HDD handling to the SSD-only AHCI driver, by separately dealing with
spin-up and link-up.
Signed-off-by: Marc Jones <marc.jones@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Note: These are timeout values and not delay values, so the event being
timed out will complete whenever it is actually ready, with a
measurement granularity of 1 millisecond, up till the timeout value.
Therefore, there is no effect on SSD booting.
The values were determined by instrumenting the code and measuring the
actual time taken by several different models of HDD for each of the
parameters and then adding 50% more for the spinup value and just
doubling the command timeout value.
Signed-off-by: Walter Murphy <wmurphy@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Exynos5 automatically performs DMA when the SATA controller executes
commands. This adds the necessary dcache-to-memory flush &
invalidation calls to allow the DMA to properly function.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Update the assignment of various physical memory buffers used by the
SATA controller to explicitly be denoted as physical addresses.
The memory is identity-mapped, so these function calls are a nop, but
they provide good semantic documentation for any maintainers.
The return value of virt_to_phys() is 'unsigned long'. On machines
where sizeof(unsigned long) != sizeof(pointer), a cast through
(uintptr_t) is needed to appease the compiler due to the potential of
losing the upper 32 bits of the address.
In compilation this scenario, a physical address could be 64-bits, yet
the C pointer environment only allows 32-bit addresses; the constraint
is that pointers cannot address more than 4Gb of memory and if
virt_to_phys() ever returns an out-of-range value for the physical
address, there are issues with emmory mapping which must be solved.
However, since the memory is identify mappeed, there is no problem
introducing the cast: the original pointer will reside in 32-bits, so
the physical address will also be within in 32-bits.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This fixes a spelling error in a message which can be output to the
console.
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This cleanup replaces the hardcoded use of '20', which represents the
number of bytes in the FIS, with sizeof(fis).
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
In the structure returned by the ATA identify device command, there are two
fields which describe the device capacity. One is a 32 bit data type which
reports the number of sectors as a 28 bit LBA, and the other is a 64 bit data
type which is for a 48 bit LBA. If the device doesn't support 48 bit LBAs,
the small value is the only value with the correct size. If it supports more,
if the number of sectors is small enough to fit into 28 bits, both fields
reflect the correct value. If it's too large, the smaller field has 28 bits of
1s, 0xfffffff, and the other field has the correct value.
The AHCI driver is implemented by attaching to the generic SCSI code and
translating on the fly between SCSI binary data structures and AHCI data
structures. It responds to requests to execute specific SCSI commands by
executing the equivalent AHCI commands and then crafting a response which
matches what a SCSI disk would send.
The AHCI driver now considers both fields and chooses the correct one when
implementing both the SCSI READ CAPACITY (10) and READ CAPACITY (16) commands.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The "scsi write" command requires support from underlying driver.
This CL enables SCSI_WRITE10 in AHCI driver.
Tested in U-Boot console, try to i/o with sector #64:
scsi read 1000 40 1
md.b 1000 200 # check if things are not 0xcc
mw.b 1000 cc 200 # try to fill with 0xcc
scsi write 1000 40 1
mw.b 1000 0 200 # fill with zero
md.b 1000 200 # should be all 0
scsi read 1000 40 1
md.b 1000 200 # should be all 0xcc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
This command doesn't really do anything when talking to a SATA device, and
sending it confuses some of them. This change makes sending the command
optional, and defaults to not. The situations where it should be sent are not
the common case.
With the standard SSD in the machine, here are some times with the option
turned off:
1. 8277
2. 8273
3. 8050
And turned on:
1. 8303
2. 8155
3. 8276
Sending that command seems to have no meaningful effect on performance.
This fixes problems with an SSD marked Toshiba NV6424, Taiwan 11159AE P
and TC58NVG5D2FTA10.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Taylor Hutt <thutt@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
- print the correct speed
- print all the AHCI capability flags
(information taken from Linux kernel driver)
- clean up some comments
For example, this might show the following string:
AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3 impl SATA mode
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Ready: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
- remove unused ssleep macro
- add some useful debugging information
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
The existing code waits a whole second for the AHCI controller to reset.
Instead, let's poll the status register to see if the reset has
succeeded and return earlier if possible. This brings down the time for
AHCI probing from 1s to 20ms.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
With an Intel AHCI controller, the driver does not operate properly
if the requested amount of blocks to read exceeds 255.
It is probably possible to specify 0 as the block count and the driver
will read 256 blocks, but it was decided to limit the number of blocks
read at once to 128 (it should be a power of 2 for the optimal
performance of solid state drives).
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
- block_dev_desc_t says that block_(read|write) take lbaint_t for blkcnt
not ulong.
- We also move the extern of sata_dev_desc into <sata.h>
- Remove now duplicate declarations from driver-specific headers.
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
sata_write() takes a const void as the last argument. Fixing this means
we also need to make ata_low_level_rw_lba{28,48} also take a const void.
Signed-off-by: Tom Rini <trini@ti.com>
- sata_write() takes a const void as the last argument. Fixing this
means we also need to make ata_low_level_rw_lba{28,48} also take a
const void.
- Both sata_{read,write} take lbaint_t for blkcnt and ulong for blknr
Signed-off-by: Tom Rini <trini@ti.com>
sata_write() takes a const void as the last argument. Fixing this means
we also need to make ata_low_level_rw_lba{28,48} also take a const void.
Acked-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
We set sata_curr_device to 0 right after returning from init_sata(), so there's
no point in setting it to the last scanned driver at this point.
Note: there are more duplicities with cmd_sata, but those might be required,
as the code seems to reset the entire controller on every scan, ignoring the
requested port number.
Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com>
Use CONFIG parameters only at one location to simplify
the code. Also create ace_readw/writew functions.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Drop mdelay() macros since we already have a common mdelay() func.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
This driver is part of Freescale's LTIB for
MX5 / MX6.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Terry Lv <r65388@freescale.com>
CC: Fabio Estevam <fabio.estevam@freescale.com>
CC: Dirk Behme <dirk.behme@de.bosch.com>
pata_bfin.c: In function 'bfin_ata_identify':
pata_bfin.c:887:2: warning: format '%x' expects type 'unsigned int',
but argument 2 has type 'lbaint_t'
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Consider that ide_preinit() succeed if at least one port is successfully
initialized. This allows to iniatialize IDE support on a board with two
SATA ports but a single hard disk available.
Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Fix:
sata_dwc.c: In function 'scan_sata':
sata_dwc.c:535:38: warning: variable 'udma_mask' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Kazuaki Ichinohe <kazuichi@fsi.co.jp>
On the P1022/P1013, the work-around for erratum SATA_A001 was implemented
only if U-Boot initializes SATA, but SATA is not initialized by default. So
move the work-around to the CPU initialization function, so that it's always
executed on the SOCs that need it.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fix:
sata_dwc.c: In function 'sata_dwc_softreset':
sata_dwc.c:444:5: warning: variable 'status' set but not used [-Wunused-but-set-variable]
sata_dwc.c:443:6: warning: variable 'serror' set but not used [-Wunused-but-set-variable]
sata_dwc.c: In function 'scan_sata':
sata_dwc.c:654:16: warning: variable 'lba_desc' set but not used [-Wunused-but-set-variable]
sata_dwc.c:538:16: warning: variable 'xfer_mask' set but not used [-Wunused-but-set-variable]
sata_dwc.c: In function 'ata_dev_read_id':
sata_dwc.c:747:14: warning: variable 'reason' set but not used [-Wunused-but-set-variable]
sata_dwc.c: In function 'ata_dev_read_sectors':
sata_dwc.c:1810:6: warning: variable 'rc' set but not used [-Wunused-but-set-variable]
sata_dwc.c: In function 'ata_dev_write_sectors':
sata_dwc.c:1994:6: warning: variable 'rc' set but not used [-Wunused-but-set-variable]
Signed-off-by: Stefan Roese <sr@denx.de>
Fix:
sym53c8xx.c: In function 'scsi_write_dsp':
sym53c8xx.c:456:16: warning: variable 'val' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Wolfgang Denk <wd@denx.de>
Fix:
ahci.c: In function 'ata_scsiop_read10':
ahci.c:564:6: warning: variable 'lba' set but not used [-Wunused-but-set-variable]
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
sata_sil3114.c: In function 'sata_identify':
sata_sil3114.c:174: warning: format '%x' expects type 'unsigned int', but
argument 2 has type 'lbaint_t'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
ahci.c: In function 'ahci_port_start':
ahci.c:401: warning: format '%x' expects type 'unsigned int', but argument 2 has
type 'struct ahci_cmd_hdr *'
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
There are several mdelay() definitions in the driver and
board code. Remove them all and provide a common mdelay()
in lib/time.c.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Add the Silicon Image series PCI Express to
Serial ATA controller support, including Sil3132,
Sil3131 and Sil3124.
The SATA controller can be used to load kernel.
The features list:
- Supports 1-lane 2.5 Gbit/s PCI Express
- Supports one/two/four independent Serial ATA channels
- Supports Serial ATA Generation 2 transfer rate of 3.0 Gbit/s
- Supports LBA28 and LBA48
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: Aaron Williams <Aaron.Williams@cavium.com>
Tested-by: Lan Chunhe <b25806@freescale.com>
If CONFIG_LBA48 is not defined, the element lba48 of struct sata_dev_desc
is not avaible, and can't be used.
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
There was a mix of UTF-8 and ISO-8859 files in the U-Boot source
tree, which could cause issues with the patchwork review system.
This commit converts all ISO-8859 files to UTF-8.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
If we don't want to build support for any partition types we can now
add #undef CONFIG_PARTITIONS in a board config file to keep this from
being compiled in. Otherwise boards assume this is compiled in by
default
Signed-off-by: Matthew McClintock <msm@freescale.com>
Before the actual initialization do a hard reset of the SATA port and the
connected device.
changes v1->v2:
- add comment for udelay
Signed-off-by: Michael Walle <michael@walle.cc>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Faraday's ftide020_s is an IDE-AHB controller for SoC design.
This patch add the u-boot driver (PIO) of ftide020 ATA (IDE) driver.
IDE commands include read, info, and other functions has been implemented.
Because this IDE controller support AHB interface only which is differ
from other most IDE controller supports PCI interface. Some registers
access is required during CMD/DATA I/O. Hence a configuration
"CONFIG_IDE_AHB" is required to be defined according to the feature in
cmd_ide.c.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
Drop warnings due to unused variables.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Marc Jones
Walter Murphy
Taylor Hutt
Gabe Black
Hung-Te Lin
Stefan Reinauer
Vadim Bendebury
Pavel Herrmann
Tom Rini
Michal Simek
Anatolij Gustschin
Marek Vasut
Stefano Babic
Mike Frysinger
Simon Guinot
Wolfgang Denk
Timur Tabi
Macpaul Lin
Stefan Roese
Kumar Gala
Marek Vasut
Tang Yuantian
Albert ARIBAUD
Graeme Russ
Matthew McClintock
Rob Herring
Michael Walle