The new MPC8360EMDS board changes the oscillator to 33.33MHz
in order to support QE 500MHz since 2008.
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Add support for the MATRIX VISION mvBlueLYNX-X, an OMAP3-based
intelligent camera.
Signed-off-by: Michael Jones <michael.jones@matrix-vision.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
- DM368 SOC
- booting with spl not with UBL from TI
- before loading u-boot from NAND into RAM, test
the RAM with the post memory test. If error
is found, switch all LEDs on and halt system.
- SPI Flash
Dataflash Typ: M25PE80
- Ethernet DM9161BI
- MMC
- USB
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Sandeep Paulraj <s-paulraj@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Adding a DMA library to the SPL. It is used if CONFIG_SPL_DMA_SUPPORT is
defined.
Signed-off-by: Simon Schwarz <simonschwarzcor@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This adds support for a new environment variable called 'fdtcontroladdr'. If
defined, the hex address is used as the address of the control fdt for U-Boot.
Note: I have not changed CONFIG_PRAM section as I already have an
outstanding patch on that.
Signed-off-by: Simon Glass <sjg@chromium.org>
This new option allows U-Boot to embed a binary device tree into its image
to allow run-time control of peripherals. This device tree is for U-Boot's
own use and is not necessarily the same one as is passed to the kernel.
The device tree compiler output should be placed in the $(obj)
rooted tree. Since $(OBJCOPY) insists on adding the path to the
generated symbol names, to ensure consistency it should be
invoked from the directory where the .dtb file is located and
given the input file name without the path.
This commit contains my entry for the ugliest Makefile / shell interaction
competition.
Signed-off-by: Simon Glass <sjg@chromium.org>
This macro is used to allocate cache line size aligned stack
buffers for use with DMA hardware.
Signed-off-by: Anton Staaf <robotboy@chromium.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Aneesh V <aneesh@ti.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
The board stopped building some time ago, and the board maintainer
agrtees to drop it - see
http://article.gmane.org/gmane.comp.boot-loaders.u-boot/112674
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Alex Dubov <oakad@yahoo.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Kumar Gala <galak@kernel.crashing.org>
Remove MK_STR from places that consume CONFIG_BOOTFILE to force all definitions to be string literals.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Documents and READMEs for NDS32 architecture.
It patch also provides usage of SoC AG101 and board ADP-AG101.
Signed-off-by: Macpaul Lin <macpaul@andestech.com>
This adds required header files for the sandbox architecture, and a basic
description of what sandbox is (README.sandbox).
Signed-off-by: Simon Glass <sjg@chromium.org>
Add pxe command, which is intended to mimic PXELINUX functionality.
'pxe get' uses tftp to retrieve a file based on UUID, MAC address or IP
address. 'pxe boot' interprets the contents of PXELINUX config like file
to boot using a specific initrd, kernel and kernel command line.
This patch also adds a README.pxe file - see it for more details on the
pxe command.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
This will be used first by the pxe code, but is intended to be
generic and reusable for other jobs in U-boot.
Signed-off-by: Jason Hobbs <jason.hobbs@calxeda.com>
Interactive DDR debugging provides a user interface to view and modify SPD,
DIMM parameters, board options and DDR controller registers before DDR is
initialized. With this feature, developers can fine-tune DDR for board
bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header
file and set an environment variable to activate it. Syntax:
setenv ddr_interactive on
After reset, U-boot prompts before initializing DDR controllers
FSL DDR>
The available commands are
print print SPD and intermediate computed data
reset reboot machine
recompute reload SPD and options to default and recompute regs
edit modify spd, parameter, or option
compute recompute registers from current next_step to end
next_step shows current next_step
help this message
go program the memory controller and continue with u-boot
The first command should be "compute", which reads data from DIMM SPDs and
board options, performs the calculation then stops before setting DDR
controller. A user can use "print" and "edit" commands to view and modify
anything. "Go" picks up from current step with any modification and
compltes the calculation then enables the DDR controller to continue u-boot.
"Recompute" does it over from fresh reading.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This is long over due. All but two net drivers have been converted, but
those have now been dropped.
The only thing left to do is actually delete all references to NET_MULTI
and code that is compiled when that is not defined. So here we scrub the
core code.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Now that we've got boards.cfg and most people have converted over,
start warning people who have yet to so we can phase board configs
completely out of the Makefile.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
These commands should work around various "hardware" ECC and BCH methods.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
[scottwood@freescale.com: s/write the page/access the page/]
Signed-off-by: Scott Wood <scottwood@freescale.com>
DDR2 has different ODT table and values. Adding table according to Samsung
application note.
Fix additive latency calculation to avoid interger underflow.
Also converted typedef dynamic_odt_t to struct dynamic_odt.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The following boards share a common design but with minor variations
between them:
P1020MSBG-PC
P1020RDB-PC
P1020UTM-PC
P1021RDB-PC
P1024RDB
P1025RDB
P2020RDB-PC
The P1020RDB-PC shares its roots in the existing P1020RDB board design,
however uses DDR3 instead of DDR2.
P2020RDB-PC differs from the P102x RDB-PC with 64-bit DDR and 100Mhz SYSCLK.
Key features on these boards include:
* DDR3
* NOR flash
* NAND flash (on RDB's only)
* SPI flash (on RDB's only)
* SDHC/MMC card slot
* VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
* PCIE slot and mini-PCIE slots
As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported
with this approach. ODT option is forced to fit this set of boards, again
because they don't have regular DIMMs.
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet
specification for writing timing.
VSC firmware Address is defined by default in config file for eTSEC1.
SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.
Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC
have pins multiplexing. QE function needs to be disabled to access Nor Flash
and CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below
'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Zhao Chenhui <b26998@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Tang Yuantian <b29983@freescale.com>
Signed-off-by: ramneek.mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
Signed-off-by: Akhil Goyal <akhil.goyal@freescale.com>
This is a trivial fix in the documentation, which corrects
board_init_r() source reference.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
This patch contains the generic changes required after
change to generic API in the previous patch.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marek.vasut@gmail.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
c2dd0d4554 added dcache_enable()
to board_init_r(). This enables d-cache for all ARM boards.
As a result some of the arm boards that are not cache-ready
are broken. Revert this change and allow platform code to
take the decision on d-cache enabling.
Also add some documentation for cache usage in ARM.
Signed-off-by: Aneesh V <aneesh@ti.com>
Marek Vasut
Jerry Huang
Michael Jones
Heiko Schocher
Simon Schwarz
Simon Glass
Anton staaf
Wolfgang Denk
Joe Hershberger
Macpaul Lin
Jason Hobbs
York Sun
Mike Frysinger
Li Yang
Albert ARIBAUD
Vladimir Zapolskiy
Sanjeev Premi
Aneesh V