This patch streamlines the differences between the MX23 and MX28 by
implementing a few helper functions to handle different DMA channel
mapping, different clock domain for SSP block and fixes a few minor
bugs.
First of all, the DMA channel mapping is now fixed in dma.h by defining
the actual channel map for both MX23 and MX28. Thus, MX23 now does no
longer use MX28 channel map which was wrong. Also, there is a fix for
MX28 DMA channel map, where the last four channels were incorrect.
Next, because correct DMA channel map is in place, the mxs_dma_init_channel()
call now bases the channel ID starting from SSP port #0. This removes the
need for DMA channel offset being added and cleans up the code. For the
same reason, the SSP0 offset can now be used in mxs_dma_desc_append(), thus
no need to adjust dma channel number in the driver either.
Lastly, the SSP clock ID is now retrieved by calling mxs_ssp_clock_by_bus()
which handles the fact that MX23 has shared SSP clock for both ports, while
MX28 has per-port SSP clock.
Finally, the mxs_ssp_bus_id_valid() pulls out two implementations of the
same functionality from MMC and SPI driver into common code.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
Rename all i.MX6 pad declarations to MX6_PAD_x, so a board
may support either i.MX6Quad/Dual (MX6Q) or i.MX6Dual-Lite/Solo
(MX6DL) by including the proper header.
Boards mx6qarm2, mx6qsabreauto, mx6qsabrelite, and mx6qsabresd
only support MX6Q, so they include mx6q_pins.h.
Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
The differences include the number of GPIOs and that one is
not required to set the pinmux on request.
Signed-off-by: Holger Hans Peter Freyther <holger@freyther.de>
This patch adds a function to set ps_hold data driving value high.
This enables the machine to stay powered on even after the initial
power-on condition goes away(e.g. power button).
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch adds BOOT_DEVICE define for USB booting and fixes
spl_board_init function to call arch_misc_init (this is the place there
musb is initialized).
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
The pinmux was generated from linux/arch/arm/mach-davinci/da830.c as of
kernel version 3.7.5. If the driver is used for the da850, then SoC
variant must be specified by CONFIG_SOC_DA850.
Signed-off-by: Tomas Novotny <tomas@novotny.cz>
Cc: Tom Rini <trini@ti.com>
On a mx6qsabresd revision C board with rev1.2 mx6q, the system gets resetted
and it is not able to reach the Linux prompt.
Comparing the watchdog behaviour on a revB versus revC board:
- On a mx6qsabresd revB:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: WDOG
...
- On a mx6qsabresd revC:
U-Boot > reset
resetting ...
U-Boot 2013.01-10524-g432a3aa-dirty (Feb 07 2013 - 13:34:46)
CPU: Freescale i.MX6Q rev1.1 at 792 MHz
Reset cause: POR
So due to revC POR/watchdog circuitry whenever a watchdog occurs, it causes a POR.
Clearing the PDE - Power Down Enable bit of WMCR registers fixes the problem and
is also safe for all mx6 boards.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Common Tegra files are in arch-tegra, shared between T20/T30/T114.
Tegra114-specific headers are in arch-tegra114. Note that some of
these will be filled in as more T114 support is added (drivers,
WB/LP0 support, etc.).
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Add driver for tegra SPI "SLINK" style driver. This controller is
similar to the tegra20 SPI "SFLASH" controller. The difference is
that the SLINK controller is a genernal purpose SPI controller and the
SFLASH controller is special purpose and can only talk to FLASH
devices. In addition there are potentially many instances of an SLINK
controller on tegra and only a single instance of SFLASH. Tegra20 is
currently ths only version of tegra that instantiates an SFLASH
controller.
This driver supports basic PIO mode of operation and is configurable
(CONFIG_OF_CONTROL) to be driven off devicetree bindings. Up to 4
devices per controller may be attached, although typically only a
single chip select line is exposed from tegra per controller so in
reality this is usually limited to 1.
To enable this driver, use CONFIG_TEGRA_SLINK
Signed-off-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add I/O addresses of SPI SLINK controllers 1-6
Signed-off-by: Allen Martin <amartin@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
FUNCMUX_ defines should be named after the pin groups they affect, not
after the module they're muxing onto those pin groups.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This 'commonizes' much of the clock/pll code. SoC-dependent code
and tables are left in arch/cpu/tegraXXX-common/clock.c
Some T30 tables needed whitespace fixes due to checkpatch complaints.
Signed-off-by: Tom Warren <twarren@nvidia.com>
AM335x EVM 1.5A uses Micron MT41J512M8RH-125 SDRAM 4Gb (512Mx8) as the
DDR3 chip.
[Hebbar Gururaja <gururaja.hebbar@ti.com>]
- Resolve merge conflict while rebasing. File structure is
changed in the mainline. So re-arrange the code accordingly.
- Update commit message to reflect the DDR3 part number
Signed-off-by: Jeff Lance <j-lance1@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Hebbar Gururaja <gururaja.hebbar@ti.com>
The board is named pcm051 and has this hardware:
SOC: TI AM3359
DDR3-RAM: 2x MT41J256M8HX-15EIT:D 512MiB
ETH 1: LAN8710AI
SPI-Flash: W25Q64BVSSIG
RTC: RV-4162-C7
I2C-EEPROM: CAT32WC32
NAND: MT29F4G08_VFPGA63
PMIC: TPS65910A3
LCD
Supported:
UART 1
MMC/SD
ETH 1
USB
I2C
SPI
Not yet supported:
NAND
RTC
LCD
Signed-off-by: Lars Poeschel <poeschel@lemonage.de>
[trini: Add #define CONFIG_PHY_ADDR 0 to config]
Signed-off-by: Tom Rini <trini@ti.com>
The patch provides slcr base address initialization support
and a support to reset the cpu through slcr driver,
hence removed the reset_cpu() from board.c.
Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move these fields into arch_global_data and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Address tlb_size in this patch as well]
Signed-off-by: Tom Rini <trini@ti.com>
We plan to move architecture-specific data into a separate structure so
that we can make the rest of it common.
As a first step, create struct arch_global_data to hold these fields.
Initially it is empty.
This patch applies to all archs at once. I can split it if this is really
a pain.
Signed-off-by: Simon Glass <sjg@chromium.org>
Some MXS based boards do not implement the card-detect signal. Allow
user to specify alternate card-detect implementation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The MX23 SSP register layout differs from MX28 in certain bits,
adjust the register layout accordingly.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The MX23 has less channels for the APBH DMA, sligtly different register
layout and some bits in those registers are placed differently. Reflect
this in the driver. This patch fixes MMC/DMA issue on MX23.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
The MX23 has different handling of the SSP clock and GPMI NAND clock sources,
add necessary quirks into the clock code to properly handle these.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Add information to identify i.MX23 chips and its known revisions.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Add register definitions for the i.MX23 power control block and
clock control block. These are essential for the basic bootstrap
of the i.MX23. Also, properly include them in imx-regs.h .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Stefano Babic <sbabic@denx.de>
This has been copied from Linux source at revision 786f02b719f.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
This adds the base addresses of i.MX23 and easy the detection of wrong
order in board setup, in case no SoC has been set, an error is raised
during build.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Create function which converts SSP bus number to SSP register pointer.
This functionality is reimplemented multiple times in the code, thus
make one common implementation. Moreover, make it a switch(), since the
SSP ports are not mapped in such nice linear fashion on MX23, therefore
having it a switch will simplify things there.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andy Fleming <afleming@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
IRDA is a synonym for UARTB in tegra pinmux, remove all usage of this
synonym and replace with UARTB to disambiguate.
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Add 16-bit divider support (I2C) to periph table, annotate and
correct some entries, and fix clk_id lookup function.
Signed-off-by: Tom Warren <twarren@nvidia.com>
These files are used by both SPL and main U-Boot.
Also made minor changes to shared Tegra code to support
T30 differences.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Common Tegra files are in arch-tegra, shared between T20 and T30.
Tegra30-specific headers are in arch-tegra30. Note that some of
these will be filled in as more T30 support is added (drivers,
WB/LP0 support, etc.). A couple of Tegra20 files were changed
to support common headers in arch-tegra, also.
Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Marek Vasut
Eric Nelson
Holger Hans Peter Freyther
Rajeshwari Shinde
Ilya Yanok
Tomas Novotny
Fabio Estevam
Tom Warren
Allen Martin
Stephen Warren
Tom Warren
Jeff Lance
Lars Poeschel
Michal Simek
Simon Glass
Rob Herring
Otavio Salvador