The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.
The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.
Signed-off-by: Stefano Babic <sbabic@denx.de>
Using seperate function calls for each bit-bang of slave serial
load can be painfully slow. This patch adds the possibility to
supply a block write function that loads the complete block of
data in one call (like it can already be done with Altera FPGAs).
On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load
time from around 15 seconds to around 3 seconds
Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
PPC boards are the only users of the current FPGA code which is littered
with manual relocation fixups. Now that proper relocation is supported
for PPC boards, remove FPGA manual relocation.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This patch does some minor fixing of the Xilinx Spartan III
FPGA boot code:
- Fixed call order of post configuration callback and
success message printing (result of copy-paste?)
- remove obsolete comment
- minor coding style cleanup
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
This patch does some minor fixing of the Xilinx Spartan II
FPGA boot code:
- Fixed call order of post configuration callback and
success message printing (result of copy-paste?)
- relocate post configuration callback only when it
is implemented
- remove obsolete comment
- minor coding style cleanup
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Stefano Babic
Wolfgang Wegner
Peter Tyser
Matthias Fuchs
Jean-Christophe PLAGNIOL-VILLARD