3 Commits (5800e7ab32c200836e81ab2384817d93105561c5)

Author	SHA1	Message	Date
york	076bff8f47	powerpc/8xxx: Fix bug in memctrl interleaving & bank interleaving on cs0~cs4 ... Verified on MPC8641HPCN with four DDR2 dimms. Each dimm has dual rank with 512MB each rank. Also check dimm size and rank size for memory controller interleaving Signed-off-by: York Sun <yorksun@freescale.com>	15 years ago
Kumar Gala	79e4e6480b	powerpc/8xxx: Enabled hwconfig for memory interleaving ... Replace environmental variables memctl_intlv_ctl and ba_intlv_ctl with hwconfig parameters. The syntax is setenv hwconfig "fsl_ddr:ctlr_intlv=<mode>,bank_intlv=<mode>" The mode values for memory controller interleaving are cacheline page bank superbank The mode values for bank interleaving are cs0_cs1 cs2_cs3 cs0_cs1_and_cs2_cs3 cs0_cs1_cs2_cs3 Signed-off-by: York Sun <yorksun@freescale.com>	15 years ago
Haiying Wang	c9ffd839b1	Check DDR interleaving mode ... * Check DDR interleaving mode from environment by reading memctl_intlv_ctl and ba_intlv_ctl. * Print DDR interleaving mode information * Add doc/README.fsl-ddr to describe the interleaving setting Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>	17 years ago