Commit Graph

3 Commits (69e8d4ba7f183fcde32ffff1f3136cd10c30dda9)

Author SHA1 Message Date
Chin Liang See 89a54abf1b ddr: altera: Configuring SDRAM extra cycles timing parameters 9 years ago
Marek Vasut f6badb0d89 arm: socfpga: Switch to filtered QTS files 10 years ago
Marek Vasut ca62d2e1fc arm: socfpga: Move wrappers into platform directory 10 years ago
Marek Vasut 042ff2d0fa ddr: altera: sequencer: Wrap misc remaining macros 10 years ago
Marek Vasut 10c14261f3 ddr: altera: sequencer: Wrap IO_* macros 10 years ago
Marek Vasut d718a26b0c ddr: altera: sequencer: Wrap RW_MGR_* macros 10 years ago
Marek Vasut 04955cf247 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init 10 years ago
Marek Vasut 5af914189e ddr: altera: sdram: Introduce socfpga_sdram_get_config() 10 years ago