Your ROOT_URL in app.ini is https://src.whiteboxsystems.nl/ but you are visiting http://src.whiteboxsystems.nl/Whitebox/u-boot/commits/commit/7f0cfe478bd817d2bb373522222cf06630fea3cd/common/ddr_spd.c You should set ROOT_URL correctly, otherwise the web may not work correctly.

6 Commits (7f0cfe478bd817d2bb373522222cf06630fea3cd)

Author	SHA1	Message	Date
Tom Rini	5b8031ccb4	Add more SPDX-License-Identifier tags ... In a number of places we had wordings of the GPL (or LGPL in a few cases) license text that were split in such a way that it wasn't caught previously. Convert all of these to the correct SPDX-License-Identifier tag. Signed-off-by: Tom Rini <trini@konsulko.com>	9 years ago
York Sun	34e026f9b1	driver/ddr/fsl: Add DDR4 support to Freescale DDR driver ... Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>	11 years ago
Kyle Moffett	c7fd27ccfb	mpc8xxx: DDR2/DDR3: Clean up DIMM-type switch statements ... The numeric constants in the switch statements are replaced by #defines added to the common ddr_spd.h header. This dramatically improves the readability of the switch statments. In addition, a few of the longer lines were cleaned up, and the DDR2 type for an SO-RDIMM module was added to the DDR2 switch statement. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Kim Phillips <kim.phillips@freescale.com> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	14 years ago
York Sun	bcb6c2bb84	Enabled support for Rev 1.3 SPD for DDR2 DIMMs ... SPD has minor change from Rev 1.2 to 1.3. This patch enables Rev 1.3. The difference has ben examined and the code is compatible. Speed bins is not verified on hardware for CL7 at this moment. This patch also enables SPD Rev 1.x where x is up to "F". According to SPD spec, the lower nibble is optionally used to determine which additinal bytes or attribute bits have been defined. Software can safely use defaults. However, the upper nibble should always be checked. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	15 years ago
Dave Liu	c360ceac02	fsl-ddr: add the DDR3 SPD infrastructure ... - support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>	16 years ago
James Yang	0f2cbe3f5e	Add proper SPD definitions for DDR1/2/3 ... Also adds helper functions for DDR1/2 to verify the checksum. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>	17 years ago