Commit Graph

5 Commits (ae5d8f613cec1a6af7bf1fc9c42a3b856f021023)

Author SHA1 Message Date
Dave Liu b4983e16d1 fsl-ddr: use the 1T timing as default configuration 17 years ago
Ed Swarthout 7008d26a40 fsl ddr skip interleaving if not supported. 17 years ago
Haiying Wang c9ffd839b1 Check DDR interleaving mode 17 years ago
Haiying Wang dfb49108e4 Pass dimm parameters to populate populate controller options 17 years ago
Kumar Gala 58e5e9aff1 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. 17 years ago