4 Commits (b7b3b8c6a0bfc87047cb18a7abfa06fb6e9d0331)

Author	SHA1	Message	Date
Tang Yuantian	a7787b7850	fsl/sleep: updated the deep sleep framework for QorIQ platforms ... With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>	11 years ago
York Sun	f80d6472b4	driver/ddr/fsl: Fix DDR4 driver ... When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>	11 years ago
York Sun	8340e7ac86	driver/ddr: Fix DDR4 driver for ARM ... Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>	11 years ago
York Sun	34e026f9b1	driver/ddr/fsl: Add DDR4 support to Freescale DDR driver ... Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>	11 years ago
York Sun	4e5b1bd0df	driver/ddr: Change Freescale ARM DDR driver to support both big and little endian ... Initially it was believed the DDR controller on Freescale ARM would have big endian. But some platform will have little endian. Signed-off-by: York Sun <yorksun@freescale.com>	11 years ago
York Sun	9ac4ffbde1	Driver/DDR: Add Freescale DDR driver for ARM ... Make PowerPC specific code conditional so ARM SoCs can reuse this driver. Add DDR3 driver for ARM. Signed-off-by: York Sun <yorksun@freescale.com>	12 years ago