Linux understands "host" (default), "peripheral" and "otg" (broken).
Though, U-Boot doesn't restrict dr_mode variable to these values (think
of renames in future).
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
With the original value of 1/2 clock cycle delay, the system ran relatively
stable except when we run benchmarks that are intensive users of memory.
When I run samba connected disk with a HDBENCH test, the system locks-up
or reboots sporadically.
Signed-off by: Joe D'Abbraccio <Joe.D'abbraccio@freescale.com>
The device trees for these boards describe PCI I/O as starting from
address zero from the device's perspective.
Placing I/O elsewhere may cause problems with certain PCI boards, and may
cause problems with Linux.
Signed-off-by: Scott Wood <scottwood@freescale.com>
At least on the "33MHz Pilot" board crystal is actually 33.3MHz.
This patch fixes "system time drifting" problem.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Plus modify environment to use it and remove bootfile env variable,
it is internal and CONFIG_BOOTFILE is used for these purposes.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Current DDR setup easily causes memory corruption, this patch fixes it.
Also fix TIMING_CFG0_MRS_CYC definition.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
On the MPC8377ERDB: 2 SATA and 2 PCI-E.
On the MPC8378ERDB: 2 PCI-E
On the MPC8379ERDB: 4 SATA
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
There's no on-board RTC on the MPC8323ERDB, but there is an EEPROM.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
The following changes are based on kernel UCC ethernet performance:
1. Make the CSB bus pipeline depth as 4, and enable the repeat mode
2. Optimize transactions between QE and CSB. Added CFG_SPCR_OPT
switch to enable this setting.
The following changes are based on the App Note AN3369 and
verified to improve memory latency using LMbench:
3. CS0_CONFIG[AP_n_EN] is changed from 1 to 0
4. CS0_CONFIG[ODT_WR_CONFIG] set to 1. Was a reserved setting
previously.
5. TIMING_CFG_1[WRREC] is changed from 3clks to 2clks (based on
Twr=15ns, and this was already the setting in DDR_MODE)
6. TIMING_CFG_1[PRETOACT] is changed from 3clks to 2clks. (based on
Trp=15ns)
7. TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 6clks. (based on
Tras=40ns)
8. TIMING_CFG_1[ACTTORW] is changed from 3clks to 2clks. (based on
Trcd=15ns)
9. TIMING_CFG_1[REFREC] changed from 21 clks to 11clks. (based on
Trfc=75ns)
10. TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 7clks. (based
on Tfaw=50ns)
11. TIMING_CFG_2[ADD_LAT] and DDR_MODE[AL] changed from 0 to 1 (based
on CL=3 and WL=2).
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Use available shift/mask macros to define DDR configuration.
Signed-off-by: Michael Barkowski <michael.barkowski@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Update the MPC8349E-mITX, MPC8313E-RDB, and MPC837XE-RDB board files to upload
the Vitesse VSC7385 firmware. Changed CONFIG_VSC7385 to CONFIG_VSC7385_ENET.
Cleaned up the board header files to make selecting the VSC7385 easier to
control.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
The Vitesse VSC7385 is a 5-port switch found on the Freescale MPC8349E-mITX
and other boards. A small firwmare must be uploaded to its on-board memory
before it can be enabled. This patch adds the code which uploads firmware
(but not the firmware itself).
Previously, this feature was provided by a U-Boot application that was
made available only on Freescale BSPs. The VSC7385 firmware must still
be obtained separately, but at least there is no longer a need for a separate
application.
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
These defines embedded the u-boot env variables and/or the bd_t structure
in the fdt blob. The conclusion of discussion on the u-boot email list
was that embedding these in the fdt blob is not useful: there are better
ways of passing the data (in fact, the fdt blob itself replaces the
bd_t struct).
The only board that enables these is the stxxtc and they don't appear
to be used by linux.
Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Add a simple expr style command that will set an env variable as the result
of the command. This allows us to do simple math in shell. The following
operations are supported: &, |, ^, +, -, *, /.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This patch replaces the current function definitions with NESTED, LEAF
and END macro. They specify some more additional information about the
function; an alignment of symbol, type of symbol, stack frame usage, etc.
These information explicitly tells the assembler and the debugger about
the types of code we want to generate.
Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Disable default building of new uImage format support in preparation
for merge with the master. Support for new format can be enabled on
a per-board basis, by defining the following in the board's config file:
#define CONFIG_FIT 1
#define CONFIG_OF_LIBFDT 1
This can be optionally defined to give more verbose output:
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Modify the RTC API to provide one a status for the time reported by
the rtc_get() function:
0 - a reliable time is guaranteed,
< 0 - a reliable time isn't guaranteed (power fault, clock issues,
and so on).
The RTC chip drivers are responsible for providing this info if the
corresponding chip supports such functionality. If not - always
report that the time is reliable.
The POST RTC test was modified to detect the RTC faults utilizing
this new rtc_get() feature.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
- insert partition for dtb blob to TQM5200B MTD layout
- set env variables dependent on the configured board
(TQM5200 or TQM5200B)
Signed-off-by: Martin Krause <martin.krause@tqs.de>
This patch adds an fdt_next_node() function which can be used to
iterate through nodes of the tree while keeping track of depth. This
function is used to simplify the iteration code in a lot of other
functions, and is also exported for use by library users.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This patch adds an fdt_set_name() function to libfdt, mirroring
fdt_get_name(). This is a r/w function which alters the name of a
given device tree node.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
To enable this, alternative, configuration the U-Boot board configuration
file for lwmon5 includes the definitions of alternative addresses for header
(CONFIG_ALT_LH_ADDR) and buffer (CONFIG_ALT_LB_ADDR).
The Linux shall be configured with the CONFIG_ALT_LB_LOCATION option set,
and has the BOARD_ALT_LH_ADDR and BOARD_ALT_LB_ADDR constants defined in the
lwmon5 board-specific header (arch/ppc/platforms/4xx/lwmon5.h).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>
The parallel flash on the BF537-STAMP is CFI compliant, so there is no need
for the board specific driver at all. Just use the common CFI driver.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Stop tying things to the processor that should be tied to other defines and
change BFIN_CPU to CONFIG_BFIN_CPU so that it can be used in the build
system to select the -mcpu option.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
460EX doesn't support a fixed bootstrap option to boot from 512 byte page
NAND devices. The only bootstrap option for NAND booting is option F for
2k page devices. So to boot from a 512 bype page device, the I2C bootstrap
EEPROM needs to be programmed accordingly.
This patch adds basic NAND booting support for the AMCC Canyonlands aval
board and also adds support to the "bootstrap" command, to enable NAND
booting I2C setting.
Tested with 512 byte page NAND device (32MByte) on Canyonlands.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <sr@denx.de>
Wolfgang Denk
Anton Vorontsov
Joe D'Abbraccio
Scott Wood
Jerry Van Baren
Michael Barkowski
Timur Tabi
Bryan O'Donoghue
Kumar Gala
Shinya Kuribayashi
Bartlomiej Sieka
Yuri Tikhonov
Martin Krause
David Gibson
Yuri Tikhonov
Mike Frysinger
Heiko Schocher
Stefan Roese
Niklaus Giger