2 Commits (f00273a3a300d4f67bd4fa65cfc3da7b3e23819a)

Author	SHA1	Message	Date
Eugeniy Paltsev	075cbae163	ARC: HSDK: CGU: Update AXI, TUN, ARC clock options ... Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>	7 years ago
Eugeniy Paltsev	e80dac0ab8	ARC: clk: introduce HSDK CGU clock driver ... Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>	7 years ago