u-boot

Commit Graph

Author	SHA1	Message	Date
Simon Glass	72cd085aae	x86: ivybridge: Add additional LPC init Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>	11 years ago
Simon Glass	2b6051541b	x86: ivybridge: Add early LPC init so that serial works The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>	11 years ago

Author

SHA1

Message

Date

Simon Glass

72cd085aae

x86: ivybridge: Add additional LPC init

Set up all the remaining pieces of the LPC (low-pin-count) peripheral in
PCH (Peripheral Controller Hub).

Signed-off-by: Simon Glass <sjg@chromium.org>

11 years ago

Simon Glass

2b6051541b

x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>

11 years ago

2 Commits (f716bf11f3f96e487772d9e47d413c7b30f26b6c)