This patch adds support for direct NOR boot mode on
da850/omap-l138. Added da850evm_direct_nor entry in
boards.cfg to allow to build targets.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
Though Commit id a3f88293dd (da850evm:
setup the NAND flash timings) has configured the AEMIF timings, they
are not exactly in sync with the timings used in Linux. Linux is
configuring the timing register as 0x08222204, where as currently it
configured to 0x00100084 in U-Boot. This issue was found out when
support for NAND SPL is added in U-Boot. Without this patch U-Boot
does not come up with SPL.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
DA850/OMAP-L138 does not support strict MMC/SD boot mode. SPL will
be in SPI flash and U-Boot image will be in MMC/SD card. SPL will
do the low level initialization and then loads the u-boot image
from MMC/SD card.
Define CONFIG_SPL_MMC_LOAD macro in the DA850/OMAP-L138
configuration file to enable this feature.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
define SPI specific configs for SPL only when CONFIG_USE_SPIFLASH
config is defined
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
initialize baudrate, flags, data and serial initialization,
only when CONFIG_SPL_LIBCOMMON_SUPPORT is defined.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
Acked-by: Christian Riesch <christian.riesch@omicron.at>
On Logic PD Rev.3 DA850/OMAP-L138 EVM, NOR and MMC/SD cannot
work together. This patch enables the MMC/SD support only
when NOR support is disabled. NOR Flash identification works
even without this patch, but erase and write will have issues.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
AHCLKR/UART1_RTS/GP0[11] pin needs to be configured for
MMC and NOR to work on DA850/OMAP-L138 Rev.3 EVM. When
GP0[11] is low, the SD0 interface will not work, but NOR
flash will. When GP0[11] is high, SD0 will work but NOR
flash will not.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
This patch adds support for MMC/SD on DA850/OMAP-L138.
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Signed-off-by: Lad, Prabhakar <prabhakar.lad@ti.com>
Signed-off-by: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Signed-off-by: Hadli, Manjunath <manjunath.hadli@ti.com>
This patch uses the code in omap-common to support gpio modules 1-3
on am33xx based boards.
It adds base address and register definitions, enables clocks to the
modules, and enables building the common gpio code for CONFIG_AM33XX
as well as CONFIG_OMAP
Signed-off-by: Steve Sakoman <steve@sakoman.com>
UART_RESET, UART_CLK_RUNNING_MASK, and UART_SMART_IDLE_EN
are defined inn evm.c but not used. Also removes unnecessary
include of serial.h
PHYS_DRAM_1_SIZE is defined in am335x_evm.h but never used.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Fix the comment to reflect the actual function call time.
Change the printf message to look nicer in the context it might be printed.
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Parameters used for configuring certain SoC peripherals are parsed
from the cfg file and appended as part of the ais image's header. The
u-boot-spl.ais generated is flashed separately to the nand, so do not
delete the file after generation of u-boot.ais.
Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
Various devices like EEPROMs require 2-byte address support to
be properly accessed. This patch adds this support for OMAP2/3/4
I2C controller driver.
I've tested it with EEPROM (16 bit address) and TPS65217 chip
(8 bit address) on TI Beaglebone board.
Unfortunately I don't have access to any compatible hardware
with 16bit data register so I can't test if those #ifdef
clauses really work.
CC: Tom Rini <trini@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
This patch moves all bootcount implementations into a common
directory: drivers/bootcount. The generic bootcount driver
is now usable not only by powerpc platforms, but others as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Valentin Longchamp <valentin.longchamp@keymile.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Manfred Rudigier <manfred.rudigier@omicron.at>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Tested-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Tested-by: Christian Riesch <christian.riesch@omicron.at>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Frysinger <vapier@gentoo.org>
Remove old o2dnt board without OF support. New support for this board
is added by the previous patch, O2I configuration.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add common code for o2dnt and o2dnt2 based boards and add different
board configuration files for O2D, O2I, O2DNT2, O2D300, O2MNT and
O3DNT boards.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Add pci_mpc5xxx_init() prototype to the header file, so board .c files
do not need to add extern pci_mpc5xxx_init() declaration.
Signed-off-by: Anatolij Gustschin <agust@denx.de>
* 'master' of git://git.denx.de/u-boot-sh:
sh: tmu: Removed arch/sh/include/asm/clk.h
sh: tmu: Changed switch statement to shift operation
sh: tmu: Changed TMU driver using array of structures
Signed-off-by: Wolfgang Denk <wd@denx.de>
* 'sf' of git://git.denx.de/u-boot-blackfin:
sf: spansion: Add support for S25FL256S
sf: winbond: fix page_size
sf: stmicro: add support for N25Q128A
sf: stmicro: add support N25Q128 parts
sf: stmicro: support JEDEC standard two-byte signature
sf: winbond: add W25Q32
cmd_spi: remove superfluous semicolon
Signed-off-by: Wolfgang Denk <wd@denx.de>
LAW init is skipped in the SPL payload because it's assumed that the SPL
has taken care of it -- so make sure the SPL loads all the LAWs as is
done on other boards.
This bug was introduced by:
commit 4589728e21
Author: Kumar Gala <galak@kernel.crashing.org>
Date: Fri Nov 11 08:14:53 2011 -0600
powerpc/85xx: Fix builds of P1020/P2020RDB-PC_36BIT_NAND
Size grew a bit so nand-spl didn't fit in 4k, reduce done by removing
LAW entries not needed during SPL phase.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Currently the -PC variants of the P1/P2 RDB boards do not print it on boot --
e.g. a P2020RDB-PC will claim to be a plain P2020RDB. Besides being incorrect,
this can confuse a user into building U-Boot for P2020RDB rather than P2020RDB-PC,
resulting in a board that does not boot.
P1024RDB and P1025RDB are not included, as these boards apparently do not
have -PC as part of their name, even though they are supported by p1_p2_rdb_pc.
The P2020RDB variant covered by this is apparently P2020RDB-PCA rather
than P2020RDB-PC.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Instead of just shooting down the entry that covers CCSR, clear out
every TLB entry that isn't the one that we're executing out of.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Before proper environment is setup, we extract hwconfig and put it into a
buffer with size HWCONFIG_BUFFER_SIZE. We need to enlarge the buffer to
accommodate longer string. Since this macro is used in multiple files, we
move it into arch/powerpc/include/asm/config.h.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Add one more argument to call function readline_into_buffer().
Fix print SPD format for negative values.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Only the first DIMM of first controller should fall back to raw timing
parameters if SPD is missing or corrupted.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Empty slot should be skipped when calculating CAS latency.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Faster DDR3 timing requires parameters exceeding previously defined
range. Extended parameters are fixed. Added some debug messages.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Restructure DDR interleaving option to support 3 and 4 DDR controllers
for 2-, 3- and 4-way interleaving.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Required by JEDEC 79-3E for high speed DDR3.
Also change "CSn disabled" message to debug.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Some debug registers have non-zero default out of reset. If software is
not setting debug registers, skip writing to them to avoid unnecessary
overriding.
Also add debug messages for workarounds and debug registers.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
For the cores with multiple threads, we need to figure out which physical
core a thread belongs. To match the core ids, update PIR registers and
spin tables.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
In case more than 32 bit address is used, the EXT bit should be set.
Need to fix up address map for IFC #CS for 4, also need to move # of IFC
banks into config_mpc85xx.h
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
We have actual topology infomation to find out exactly which core is present.
Calculate the number of cores if not specified.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Freescale's High-End SoC are going to have Integrated Flash controller
(IFC)'s support.
So add IFC LAW target ID support for High-End SoC or corenet SoC.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG). Need to define define
CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.
Enable missed e500v2 SoC i.e. MPC8536, MPC8544, MPC8548 and MPC8572 for
debug support.
Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Lad, Prabhakar
Rajashekhara, Sudhakar
Steve Sakoman
Stefano Babic
Igor Grinberg
Sughosh Ganu
Ilya Yanok
Jeremy Andrus
Stefan Roese
Anatolij Gustschin
Wolfgang Denk
Daniel Schwierzeck
Scott Wood
Andy Fleming
York Sun
Kumar Gala
Prabhakar Kushwaha