// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP Mini Configuration * * (C) Copyright 2018, Xilinx, Inc. * * Siva Durga Prasad * Michal Simek */ /dts-v1/; / { model = "ZynqMP MINI NAND"; compatible = "xlnx,zynqmp"; #address-cells = <2>; #size-cells = <1>; aliases { serial0 = &dcc; }; chosen { stdout-path = "serial0:115200n8"; }; memory@0 { device_type = "memory"; reg = <0x0 0x0 0x40000000>; }; dcc: dcc { compatible = "arm,dcc"; status = "disabled"; u-boot,dm-pre-reloc; }; amba: amba { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges; nand0: nand@ff100000 { compatible = "arasan,nfc-v3p10"; status = "okay"; reg = <0x0 0xff100000 0x1000>; clock-names = "clk_sys", "clk_flash"; #address-cells = <2>; #size-cells = <1>; arasan,has-mdma; num-cs = <2>; partition@0 { /* for testing purpose */ label = "nand-fsbl-uboot"; reg = <0x0 0x0 0x400000>; }; partition@1 { /* for testing purpose */ label = "nand-linux"; reg = <0x0 0x400000 0x1400000>; }; partition@2 { /* for testing purpose */ label = "nand-device-tree"; reg = <0x0 0x1800000 0x400000>; }; partition@3 { /* for testing purpose */ label = "nand-rootfs"; reg = <0x0 0x1C00000 0x1400000>; }; partition@4 { /* for testing purpose */ label = "nand-bitstream"; reg = <0x0 0x3000000 0x400000>; }; partition@5 { /* for testing purpose */ label = "nand-misc"; reg = <0x0 0x3400000 0xFCC00000>; }; partition@6 { /* for testing purpose */ label = "nand1-fsbl-uboot"; reg = <0x1 0x0 0x400000>; }; partition@7 { /* for testing purpose */ label = "nand1-linux"; reg = <0x1 0x400000 0x1400000>; }; partition@8 { /* for testing purpose */ label = "nand1-device-tree"; reg = <0x1 0x1800000 0x400000>; }; partition@9 { /* for testing purpose */ label = "nand1-rootfs"; reg = <0x1 0x1C00000 0x1400000>; }; partition@10 { /* for testing purpose */ label = "nand1-bitstream"; reg = <0x1 0x3000000 0x400000>; }; partition@11 { /* for testing purpose */ label = "nand1-misc"; reg = <0x1 0x3400000 0xFCC00000>; }; }; }; }; &dcc { status = "okay"; };