upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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42 lines
929 B
42 lines
929 B
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* clk-synthesizer.h
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*
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* Clock synthesizer header
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*
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* Copyright (C) 2016, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#ifndef __CLK_SYNTHESIZER_H
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#define __CLK_SYNTHESIZER_H
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#include <common.h>
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#define CLK_SYNTHESIZER_ID_REG 0x0
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#define CLK_SYNTHESIZER_XCSEL 0x05
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#define CLK_SYNTHESIZER_MUX_REG 0x14
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#define CLK_SYNTHESIZER_PDIV2_REG 0x16
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#define CLK_SYNTHESIZER_PDIV3_REG 0x17
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#define CLK_SYNTHESIZER_BYTE_MODE 0x80
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/**
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* struct clk_synth: This structure holds data neeed for configuring
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* for clock synthesizer.
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* @id: The id of synthesizer
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* @capacitor: value of the capacitor attached
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* @mux: mux settings.
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* @pdiv2: Div to be applied to second output
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* @pdiv3: Div to be applied to third output
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*/
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struct clk_synth {
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u32 id;
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u32 capacitor;
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u32 mux;
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u32 pdiv2;
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u32 pdiv3;
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};
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int setup_clock_synthesizer(struct clk_synth *data);
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#endif
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