upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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81 lines
1.3 KiB
81 lines
1.3 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015
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* Toradex, Inc.
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*
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* Authors: Stefan Agner
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* Sanchayan Maity
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*/
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#ifndef __ASM_ARCH_VF610_DDRMC_H
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#define __ASM_ARCH_VF610_DDRMC_H
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struct ddr3_jedec_timings {
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u8 tinit;
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u32 trst_pwron;
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u32 cke_inactive;
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u8 wrlat;
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u8 caslat_lin;
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u8 trc;
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u8 trrd;
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u8 tccd;
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u8 tbst_int_interval;
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u8 tfaw;
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u8 trp;
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u8 twtr;
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u8 tras_min;
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u8 tmrd;
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u8 trtp;
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u32 tras_max;
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u8 tmod;
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u8 tckesr;
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u8 tcke;
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u8 trcd_int;
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u8 tras_lockout;
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u8 tdal;
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u8 bstlen;
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u16 tdll;
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u8 trp_ab;
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u16 tref;
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u8 trfc;
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u16 tref_int;
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u8 tpdex;
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u8 txpdll;
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u8 txsnr;
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u16 txsr;
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u8 cksrx;
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u8 cksre;
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u8 freq_chg_en;
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u16 zqcl;
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u16 zqinit;
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u8 zqcs;
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u8 ref_per_zq;
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u8 zqcs_rotate;
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u8 aprebit;
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u8 cmd_age_cnt;
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u8 age_cnt;
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u8 q_fullness;
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u8 odt_rd_mapcs0;
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u8 odt_wr_mapcs0;
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u8 wlmrd;
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u8 wldqsen;
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};
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struct ddrmc_cr_setting {
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u32 setting;
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int cr_rnum; /* CR register ; -1 for last entry */
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};
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struct ddrmc_phy_setting {
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u32 setting;
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int phy_rnum; /* PHY register ; -1 for last entry */
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};
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void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count);
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void ddrmc_phy_init(void);
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void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
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struct ddrmc_cr_setting *board_cr_settings,
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struct ddrmc_phy_setting *board_phy_settings,
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int col_diff, int row_diff);
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#endif
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