upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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42 lines
1.5 KiB
42 lines
1.5 KiB
Rockchip Dynamic Memory Controller Driver
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Required properties:
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- compatible: "rockchip,rk3399-dmc", "syscon"
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- rockchip,cru: this driver should access cru regs, so need get cru here
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- rockchip,pmucru: this driver should access pmucru regs, so need get pmucru here
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- rockchip,pmugrf: this driver should access pmugrf regs, so need get pmugrf here
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- rockchip,pmusgrf: this driver should access pmusgrf regs, so need get pmusgrf here
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- rockchip,cic: this driver should access cic regs, so need get cic here
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- reg: dynamic ram protocol controller(PCTL) address, PHY Independent(PI) address, phy controller(PHYCTL) address and memory schedule(MSCH) address
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- clock: must include clock specifiers corresponding to entries in the clock-names property.
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Must contain
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dmc_clk: for ddr working frequency
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- rockchip,sdram-params: SDRAM parameters, including all the information by ddr driver:
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Must contain
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Genarate by vendor tool and adjust for U-Boot dtsi.
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Example:
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dmc: dmc {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3399-dmc";
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devfreq-events = <&dfi>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru SCLK_DDRCLK>;
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clock-names = "dmc_clk";
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reg = <0x0 0xffa80000 0x0 0x0800
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0x0 0xffa80800 0x0 0x1800
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0x0 0xffa82000 0x0 0x2000
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0x0 0xffa84000 0x0 0x1000
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0x0 0xffa88000 0x0 0x0800
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0x0 0xffa88800 0x0 0x1800
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0x0 0xffa8a000 0x0 0x2000
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0x0 0xffa8c000 0x0 0x1000>;
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};
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&dmc {
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rockchip,sdram-params = <
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0x2
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0xa
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0x3
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...
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>;
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};
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