upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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469 lines
8.1 KiB
469 lines
8.1 KiB
/*
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* MCF5274/5 Internal Memory Map
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*
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* Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
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* Based on work Copyright (c) 2003 Josef Baumgartner
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* <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5275__
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#define __IMMAP_5275__
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#define MMAP_SCM (CFG_MBAR + 0x00000000)
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#define MMAP_SDRAM (CFG_MBAR + 0x00000040)
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#define MMAP_FBCS (CFG_MBAR + 0x00000080)
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#define MMAP_DMA0 (CFG_MBAR + 0x00000100)
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#define MMAP_DMA1 (CFG_MBAR + 0x00000110)
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#define MMAP_DMA2 (CFG_MBAR + 0x00000120)
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#define MMAP_DMA3 (CFG_MBAR + 0x00000130)
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#define MMAP_UART0 (CFG_MBAR + 0x00000200)
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#define MMAP_UART1 (CFG_MBAR + 0x00000240)
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#define MMAP_UART2 (CFG_MBAR + 0x00000280)
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#define MMAP_I2C (CFG_MBAR + 0x00000300)
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#define MMAP_QSPI (CFG_MBAR + 0x00000340)
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#define MMAP_DTMR0 (CFG_MBAR + 0x00000400)
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#define MMAP_DTMR1 (CFG_MBAR + 0x00000440)
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#define MMAP_DTMR2 (CFG_MBAR + 0x00000480)
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#define MMAP_DTMR3 (CFG_MBAR + 0x000004C0)
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#define MMAP_INTC0 (CFG_MBAR + 0x00000C00)
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#define MMAP_INTC1 (CFG_MBAR + 0x00000D00)
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#define MMAP_INTCACK (CFG_MBAR + 0x00000F00)
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#define MMAP_FEC0 (CFG_MBAR + 0x00001000)
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#define MMAP_FEC0FIFO (CFG_MBAR + 0x00001400)
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#define MMAP_FEC1 (CFG_MBAR + 0x00001800)
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#define MMAP_FEC1FIFO (CFG_MBAR + 0x00001C00)
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#define MMAP_GPIO (CFG_MBAR + 0x00100000)
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#define MMAP_RCM (CFG_MBAR + 0x00110000)
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#define MMAP_CCM (CFG_MBAR + 0x00110004)
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#define MMAP_PLL (CFG_MBAR + 0x00120000)
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#define MMAP_EPORT (CFG_MBAR + 0x00130000)
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#define MMAP_WDOG (CFG_MBAR + 0x00140000)
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#define MMAP_PIT0 (CFG_MBAR + 0x00150000)
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#define MMAP_PIT1 (CFG_MBAR + 0x00160000)
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#define MMAP_PIT2 (CFG_MBAR + 0x00170000)
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#define MMAP_PIT3 (CFG_MBAR + 0x00180000)
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#define MMAP_MDHA (CFG_MBAR + 0x00190000)
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#define MMAP_RNG (CFG_MBAR + 0x001A0000)
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#define MMAP_SKHA (CFG_MBAR + 0x001B0000)
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#define MMAP_USB (CFG_MBAR + 0x001C0000)
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#define MMAP_PWM0 (CFG_MBAR + 0x001D0000)
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/* System configuration registers
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*/
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typedef struct sys_ctrl {
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u32 ipsbar;
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u32 res1;
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u32 rambar;
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u32 res2;
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u8 crsr;
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u8 cwcr;
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u8 lpicr;
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u8 cwsr;
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u8 res3[8];
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u32 mpark;
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u8 mpr;
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u8 res4[3];
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u8 pacr0;
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u8 pacr1;
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u8 pacr2;
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u8 pacr3;
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u8 pacr4;
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u8 res5;
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u8 pacr5;
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u8 pacr6;
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u8 pacr7;
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u8 res6;
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u8 pacr8;
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u8 res7;
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u8 gpacr;
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u8 res8[3];
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} sysctrl_t;
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/* SDRAM controller registers, offset: 0x040
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*/
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typedef struct sdram_ctrl {
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u32 sdmr;
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u32 sdcr;
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u32 sdcfg1;
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u32 sdcfg2;
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u32 sdbar0;
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u32 sdbmr0;
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u32 sdbar1;
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u32 sdbmr1;
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} sdramctrl_t;
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/* Chip select module registers, offset: 0x080
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*/
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typedef struct cs_ctlr {
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u16 ar0;
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u16 res1;
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u32 mr0;
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u16 res2;
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u16 cr0;
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u16 ar1;
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u16 res3;
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u32 mr1;
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u16 res4;
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u16 cr1;
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u16 ar2;
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u16 res5;
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u32 mr2;
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u16 res6;
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u16 cr2;
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u16 ar3;
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u16 res7;
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u32 mr3;
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u16 res8;
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u16 cr3;
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u16 ar4;
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u16 res9;
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u32 mr4;
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u16 res10;
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u16 cr4;
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u16 ar5;
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u16 res11;
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u32 mr5;
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u16 res12;
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u16 cr5;
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u16 ar6;
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u16 res13;
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u32 mr6;
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u16 res14;
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u16 cr6;
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u16 ar7;
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u16 res15;
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u32 mr7;
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u16 res16;
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u16 cr7;
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} csctrl_t;
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/* DMA module registers, offset 0x100
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*/
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typedef struct dma_ctrl {
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u32 sar;
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u32 dar;
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u32 dsrbcr;
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u32 dcr;
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} dma_t;
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/* QSPI module registers, offset 0x340
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*/
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typedef struct qspi_ctrl {
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u16 qmr;
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u8 res1[2];
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u16 qdlyr;
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u8 res2[2];
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u16 qwr;
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u8 res3[2];
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u16 qir;
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u8 res4[2];
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u16 qar;
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u8 res5[2];
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u16 qdr;
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u8 res6[2];
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} qspi_t;
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/* Interrupt module registers, offset 0xc00
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*/
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typedef struct int_ctrl {
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u32 iprh0;
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u32 iprl0;
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u32 imrh0;
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u32 imrl0;
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u32 frch0;
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u32 frcl0;
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u8 irlr;
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u8 iacklpr;
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u8 res1[0x26];
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u8 icr0[64]; /* No ICR0, done this way for readability */
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u8 res2[0x60];
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u8 swiack0;
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u8 res3[3];
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u8 Lniack0_1;
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u8 res4[3];
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u8 Lniack0_2;
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u8 res5[3];
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u8 Lniack0_3;
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u8 res6[3];
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u8 Lniack0_4;
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u8 res7[3];
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u8 Lniack0_5;
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u8 res8[3];
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u8 Lniack0_6;
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u8 res9[3];
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u8 Lniack0_7;
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u8 res10[3];
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} int0_t;
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/* GPIO port registers
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*/
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typedef struct gpio_ctrl {
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/* Port Output Data Registers */
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u8 podr_res1[4];
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u8 podr_busctl;
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u8 podr_addr;
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u8 podr_res2[2];
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u8 podr_cs;
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u8 podr_res3;
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u8 podr_fec0h;
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u8 podr_fec0l;
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u8 podr_feci2c;
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u8 podr_qspi;
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u8 podr_sdram;
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u8 podr_timerh;
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u8 podr_timerl;
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u8 podr_uartl;
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u8 podr_fec1h;
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u8 podr_fec1l;
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u8 podr_bs;
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u8 podr_res4;
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u8 podr_usbh;
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u8 podr_usbl;
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u8 podr_uarth;
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u8 podr_res5[3];
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/* Port Data Direction Registers */
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u8 pddr_res1[4];
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u8 pddr_busctl;
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u8 pddr_addr;
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u8 pddr_res2[2];
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u8 pddr_cs;
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u8 pddr_res3;
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u8 pddr_fec0h;
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u8 pddr_fec0l;
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u8 pddr_feci2c;
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u8 pddr_qspi;
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u8 pddr_sdram;
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u8 pddr_timerh;
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u8 pddr_timerl;
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u8 pddr_uartl;
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u8 pddr_fec1h;
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u8 pddr_fec1l;
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u8 pddr_bs;
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u8 pddr_res4;
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u8 pddr_usbh;
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u8 pddr_usbl;
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u8 pddr_uarth;
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u8 pddr_res5[3];
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/* Port Pin Data/Set Registers */
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u8 ppdsdr_res1[4];
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u8 ppdsdr_busctl;
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u8 ppdsdr_addr;
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u8 ppdsdr_res2[2];
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u8 ppdsdr_cs;
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u8 ppdsdr_res3;
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u8 ppdsdr_fec0h;
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u8 ppdsdr_fec0l;
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u8 ppdsdr_feci2c;
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u8 ppdsdr_qspi;
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u8 ppdsdr_sdram;
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u8 ppdsdr_timerh;
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u8 ppdsdr_timerl;
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u8 ppdsdr_uartl;
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u8 ppdsdr_fec1h;
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u8 ppdsdr_fec1l;
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u8 ppdsdr_bs;
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u8 ppdsdr_res4;
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u8 ppdsdr_usbh;
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u8 ppdsdr_usbl;
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u8 ppdsdr_uarth;
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u8 ppdsdr_res5[3];
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/* Port Clear Output Data Registers */
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u8 pclrr_res1[4];
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u8 pclrr_busctl;
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u8 pclrr_addr;
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u8 pclrr_res2[2];
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u8 pclrr_cs;
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u8 pclrr_res3;
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u8 pclrr_fec0h;
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u8 pclrr_fec0l;
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u8 pclrr_feci2c;
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u8 pclrr_qspi;
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u8 pclrr_sdram;
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u8 pclrr_timerh;
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u8 pclrr_timerl;
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u8 pclrr_uartl;
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u8 pclrr_fec1h;
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u8 pclrr_fec1l;
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u8 pclrr_bs;
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u8 pclrr_res4;
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u8 pclrr_usbh;
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u8 pclrr_usbl;
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u8 pclrr_uarth;
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u8 pclrr_res5[3];
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/* Pin Assignment Registers */
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u8 par_addr;
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u8 par_cs;
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u16 par_busctl;
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u8 par_res1[2];
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u16 par_usb;
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u8 par_fec0hl;
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u8 par_fec1hl;
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u16 par_timer;
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u16 par_uart;
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u16 par_qspi;
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u16 par_sdram;
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u16 par_feci2c;
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u8 par_bs;
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u8 par_res2[3];
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} gpio_t;
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/* PWM module registers
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*/
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typedef struct pwm_ctrl {
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u8 pwcr0;
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u8 res1[3];
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u8 pwcr1;
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u8 res2[3];
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u8 pwcr2;
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u8 res3[7];
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u8 pwwd0;
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u8 res4[3];
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u8 pwwd1;
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u8 res5[3];
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u8 pwwd2;
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u8 res6[7];
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} pwm_t;
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/* Watchdog registers
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*/
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typedef struct wdog_ctrl {
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u16 wcr;
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u16 wmr;
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u16 wcntr;
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u16 wsr;
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u8 res4[114];
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} wdog_t;
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/* USB module registers
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*/
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typedef struct usb {
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u16 res1;
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u16 fnr;
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u16 res2;
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u16 fnmr;
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u16 res3;
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u16 rfmr;
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u16 res4;
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u16 rfmmr;
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u8 res5[3];
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u8 far;
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u32 asr;
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u32 drr1;
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u32 drr2;
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u16 res6;
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u16 specr;
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u16 res7;
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u16 ep0sr;
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u32 iep0cfg;
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u32 oep0cfg;
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u32 ep1cfg;
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u32 ep2cfg;
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u32 ep3cfg;
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u32 ep4cfg;
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u32 ep5cfg;
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u32 ep6cfg;
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u32 ep7cfg;
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u32 ep0ctl;
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u16 res8;
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u16 ep1ctl;
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u16 res9;
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u16 ep2ctl;
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u16 res10;
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u16 ep3ctl;
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u16 res11;
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u16 ep4ctl;
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u16 res12;
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u16 ep5ctl;
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u16 res13;
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u16 ep6ctl;
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u16 res14;
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u16 ep7ctl;
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u32 ep0isr;
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u16 res15;
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u16 ep1isr;
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u16 res16;
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u16 ep2isr;
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u16 res17;
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u16 ep3isr;
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u16 res18;
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u16 ep4isr;
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u16 res19;
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u16 ep5isr;
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u16 res20;
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u16 ep6isr;
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u16 res21;
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u16 ep7isr;
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u32 ep0imr;
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u16 res22;
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u16 ep1imr;
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u16 res23;
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u16 ep2imr;
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u16 res24;
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u16 ep3imr;
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u16 res25;
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u16 ep4imr;
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u16 res26;
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u16 ep5imr;
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u16 res27;
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u16 ep6imr;
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u16 res28;
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u16 ep7imr;
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u32 ep0dr;
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u32 ep1dr;
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u32 ep2dr;
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u32 ep3dr;
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u32 ep4dr;
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u32 ep5dr;
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u32 ep6dr;
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u32 ep7dr;
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u16 res29;
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u16 ep0dpr;
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u16 res30;
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u16 ep1dpr;
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u16 res31;
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u16 ep2dpr;
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u16 res32;
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u16 ep3dpr;
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u16 res33;
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u16 ep4dpr;
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u16 res34;
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u16 ep5dpr;
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u16 res35;
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u16 ep6dpr;
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u16 res36;
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u16 ep7dpr;
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u8 res37[788];
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u8 cfgram[1024];
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} usb_t;
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/* PLL module registers
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*/
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typedef struct pll_ctrl {
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u32 syncr;
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u32 synsr;
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} pll_t;
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typedef struct rcm {
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u8 rcr;
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u8 rsr;
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} rcm_t;
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#endif /* __IMMAP_5275__ */
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