upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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79 lines
1.4 KiB
79 lines
1.4 KiB
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot src/lib/ramtest.c
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/post.h>
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static void write_phys(unsigned long addr, u32 value)
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{
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#if CONFIG_SSE2
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asm volatile(
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"movnti %1, (%0)"
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: /* outputs */
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: "r" (addr), "r" (value) /* inputs */
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: /* clobbers */
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);
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#else
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writel(value, addr);
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#endif
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}
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static u32 read_phys(unsigned long addr)
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{
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return readl(addr);
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}
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static void phys_memory_barrier(void)
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{
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#if CONFIG_SSE2
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/* Needed for movnti */
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asm volatile(
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"sfence"
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:
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:
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: "memory"
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);
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#else
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asm volatile(""
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:
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:
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: "memory");
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#endif
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}
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void quick_ram_check(void)
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{
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int fail = 0;
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u32 backup;
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backup = read_phys(CONFIG_RAMBASE);
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write_phys(CONFIG_RAMBASE, 0x55555555);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0x55555555)
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fail = 1;
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write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
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fail = 1;
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write_phys(CONFIG_RAMBASE, 0x00000000);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0x00000000)
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fail = 1;
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write_phys(CONFIG_RAMBASE, 0xffffffff);
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phys_memory_barrier();
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if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
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fail = 1;
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write_phys(CONFIG_RAMBASE, backup);
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if (fail) {
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post_code(POST_RAM_FAILURE);
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panic("RAM INIT FAILURE!\n");
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}
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phys_memory_barrier();
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}
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