upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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58 lines
1.6 KiB
58 lines
1.6 KiB
/*
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* Copyright (c) 2008 Nuovation System Designs, LLC
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* Grant Erickson <gerickson@nuovations.com>
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*
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* Copyright (c) 2007-2009 DENX Software Engineering, GmbH
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* Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Description:
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* This file implements ECC initialization for PowerPC processors
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* using the IBM SDRAM DDR1 & DDR2 controller.
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*/
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#ifndef _ECC_H_
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#define _ECC_H_
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/*
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* Since the IBM DDR controller used on 440GP/GX/EP/GR is not register
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* compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT
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* we need to make some processor dependant defines used later on by the
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* driver.
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*/
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/* For 440GP/GX/EP/GR */
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#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)
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#define SDRAM_MCOPT1 SDRAM_CFG0
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#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK
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#define SDRAM_MCOPT1_MCHK_NON SDRAM_CFG0_MCHK_NON
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#define SDRAM_MCOPT1_MCHK_GEN SDRAM_CFG0_MCHK_GEN
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#define SDRAM_MCOPT1_MCHK_CHK SDRAM_CFG0_MCHK_CHK
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#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK
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#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK
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#define SDRAM_MCOPT1_DMWD_32 SDRAM_CFG0_DMWD_32
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#define SDRAM_MCSTAT SDRAM0_MCSTS
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#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS
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#define SDRAM_MCSTAT_IDLE_NOT SDRAM_MCSTS_IDLE_NOT
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#define SDRAM_ECCES SDRAM0_ECCESR
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#endif
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void ecc_init(unsigned long * const start, unsigned long size);
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void do_program_ecc(unsigned long tlb_word2_i_value);
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static void inline blank_string(int size)
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{
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int i;
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for (i = 0; i < size; i++)
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putc('\b');
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for (i = 0; i < size; i++)
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putc(' ');
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for (i = 0; i < size; i++)
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putc('\b');
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}
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#endif /* _ECC_H_ */
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