upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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43 lines
1.2 KiB
43 lines
1.2 KiB
/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _TEGRA30_GPIO_H_
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#define _TEGRA30_GPIO_H_
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/*
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* The Tegra 3x GPIO controller has 246 GPIOS in 8 banks of 4 ports,
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* each with 8 GPIOs.
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*/
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#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
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#define TEGRA_GPIO_BANKS 8 /* number of banks */
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#include <asm/arch-tegra/gpio.h>
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/* GPIO Controller registers for a single bank */
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struct gpio_ctlr_bank {
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uint gpio_config[TEGRA_GPIO_PORTS];
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uint gpio_dir_out[TEGRA_GPIO_PORTS];
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uint gpio_out[TEGRA_GPIO_PORTS];
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uint gpio_in[TEGRA_GPIO_PORTS];
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uint gpio_int_status[TEGRA_GPIO_PORTS];
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uint gpio_int_enable[TEGRA_GPIO_PORTS];
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uint gpio_int_level[TEGRA_GPIO_PORTS];
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uint gpio_int_clear[TEGRA_GPIO_PORTS];
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uint gpio_masked_config[TEGRA_GPIO_PORTS];
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uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
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uint gpio_masked_out[TEGRA_GPIO_PORTS];
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uint gpio_masked_in[TEGRA_GPIO_PORTS];
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uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
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uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
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uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
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uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
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};
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struct gpio_ctlr {
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struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
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};
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#endif /* _TEGRA30_GPIO_H_ */
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