upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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32 lines
886 B
32 lines
886 B
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*/
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#ifndef __MIPS_CACHE_H__
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#define __MIPS_CACHE_H__
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#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define ARCH_DMA_MINALIGN (L1_CACHE_BYTES)
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/*
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* CONFIG_SYS_CACHELINE_SIZE is still used in various drivers primarily for
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* DMA buffer alignment. Satisfy those drivers by providing it as a synonym
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* of ARCH_DMA_MINALIGN for now.
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*/
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#define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
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#ifndef __ASSEMBLY__
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/**
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* mips_cache_probe() - Probe the properties of the caches
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*
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* Call this to probe the properties such as line sizes of the caches
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* present in the system, if any. This must be done before cache maintenance
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* functions such as flush_cache may be called.
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*/
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void mips_cache_probe(void);
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#endif
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#endif /* __MIPS_CACHE_H__ */
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