upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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598 lines
18 KiB
598 lines
18 KiB
/*
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* LPC32xx SLC NAND flash controller driver
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*
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* (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
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*
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* Hardware ECC support original source code
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* Copyright (C) 2008 by NXP Semiconductors
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* Author: Kevin Wells
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*
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* Copyright (c) 2015 Tyco Fire Protection Products.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/config.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/cpu.h>
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#if defined(CONFIG_DMA_LPC32XX) && defined(CONFIG_SPL_BUILD)
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#warning "DMA support in SPL image is not tested"
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#endif
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struct lpc32xx_nand_slc_regs {
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u32 data;
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u32 addr;
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u32 cmd;
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u32 stop;
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u32 ctrl;
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u32 cfg;
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u32 stat;
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u32 int_stat;
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u32 ien;
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u32 isr;
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u32 icr;
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u32 tac;
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u32 tc;
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u32 ecc;
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u32 dma_data;
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};
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/* CFG register */
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#define CFG_CE_LOW (1 << 5)
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#define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
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#define CFG_ECC_EN (1 << 3) /* ECC enable bit */
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#define CFG_DMA_BURST (1 << 2) /* DMA burst bit */
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#define CFG_DMA_DIR (1 << 1) /* DMA write(0)/read(1) bit */
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/* CTRL register */
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#define CTRL_SW_RESET (1 << 2)
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#define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
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#define CTRL_DMA_START (1 << 0) /* Start DMA channel bit */
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/* STAT register */
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#define STAT_DMA_FIFO (1 << 2) /* DMA FIFO has data bit */
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#define STAT_NAND_READY (1 << 0)
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/* INT_STAT register */
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#define INT_STAT_TC (1 << 1)
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#define INT_STAT_RDY (1 << 0)
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/* TAC register bits, be aware of overflows */
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#define TAC_W_RDY(n) (max_t(uint32_t, (n), 0xF) << 28)
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#define TAC_W_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 24)
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#define TAC_W_HOLD(n) (max_t(uint32_t, (n), 0xF) << 20)
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#define TAC_W_SETUP(n) (max_t(uint32_t, (n), 0xF) << 16)
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#define TAC_R_RDY(n) (max_t(uint32_t, (n), 0xF) << 12)
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#define TAC_R_WIDTH(n) (max_t(uint32_t, (n), 0xF) << 8)
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#define TAC_R_HOLD(n) (max_t(uint32_t, (n), 0xF) << 4)
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#define TAC_R_SETUP(n) (max_t(uint32_t, (n), 0xF) << 0)
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/* NAND ECC Layout for small page NAND devices
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* Note: For large page devices, the default layouts are used. */
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static struct nand_ecclayout lpc32xx_nand_oob_16 = {
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.eccbytes = 6,
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.eccpos = {10, 11, 12, 13, 14, 15},
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.oobfree = {
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{.offset = 0,
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. length = 4},
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{.offset = 6,
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. length = 4}
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}
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};
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#if defined(CONFIG_DMA_LPC32XX)
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#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
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/*
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* DMA Descriptors
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* For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
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* For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
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*/
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static struct lpc32xx_dmac_ll dmalist[ECCSTEPS * 2 + 1];
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static u32 ecc_buffer[8]; /* MAX ECC size */
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static unsigned int dmachan = (unsigned int)-1; /* Invalid channel */
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/*
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* Helper macro for the DMA client (i.e. NAND SLC):
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* - to write the next DMA linked list item address
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* (see arch/include/asm/arch-lpc32xx/dma.h).
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* - to assign the DMA data register to DMA source or destination address.
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* - to assign the ECC register to DMA source or destination address.
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*/
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#define lpc32xx_dmac_next_lli(x) ((u32)x)
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#define lpc32xx_dmac_set_dma_data() ((u32)&lpc32xx_nand_slc_regs->dma_data)
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#define lpc32xx_dmac_set_ecc() ((u32)&lpc32xx_nand_slc_regs->ecc)
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#endif
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static struct lpc32xx_nand_slc_regs __iomem *lpc32xx_nand_slc_regs
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= (struct lpc32xx_nand_slc_regs __iomem *)SLC_NAND_BASE;
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static void lpc32xx_nand_init(void)
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{
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uint32_t hclk = get_hclk_clk_rate();
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/* Reset SLC NAND controller */
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writel(CTRL_SW_RESET, &lpc32xx_nand_slc_regs->ctrl);
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/* 8-bit bus, no DMA, no ECC, ordinary CE signal */
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writel(0, &lpc32xx_nand_slc_regs->cfg);
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/* Interrupts disabled and cleared */
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writel(0, &lpc32xx_nand_slc_regs->ien);
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writel(INT_STAT_TC | INT_STAT_RDY,
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&lpc32xx_nand_slc_regs->icr);
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/* Configure NAND flash timings */
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writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
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TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
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TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
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TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
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TAC_R_RDY(CONFIG_LPC32XX_NAND_SLC_RDR_CLKS) |
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TAC_R_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_RWIDTH) |
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TAC_R_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_RHOLD) |
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TAC_R_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_RSETUP),
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&lpc32xx_nand_slc_regs->tac);
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}
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static void lpc32xx_nand_cmd_ctrl(struct mtd_info *mtd,
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int cmd, unsigned int ctrl)
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{
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debug("ctrl: 0x%08x, cmd: 0x%08x\n", ctrl, cmd);
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if (ctrl & NAND_NCE)
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setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
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else
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clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_CE_LOW);
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if (cmd == NAND_CMD_NONE)
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return;
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if (ctrl & NAND_CLE)
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writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->cmd);
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else if (ctrl & NAND_ALE)
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writel(cmd & 0xFF, &lpc32xx_nand_slc_regs->addr);
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}
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static int lpc32xx_nand_dev_ready(struct mtd_info *mtd)
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{
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return readl(&lpc32xx_nand_slc_regs->stat) & STAT_NAND_READY;
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}
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#if defined(CONFIG_DMA_LPC32XX)
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/*
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* Prepares DMA descriptors for NAND RD/WR operations
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* If the size is < 256 Bytes then it is assumed to be
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* an OOB transfer
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*/
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static void lpc32xx_nand_dma_configure(struct nand_chip *chip,
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const u8 *buffer, int size,
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int read)
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{
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u32 i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
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struct lpc32xx_dmac_ll *dmalist_cur;
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struct lpc32xx_dmac_ll *dmalist_cur_ecc;
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/*
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* CTRL descriptor entry for reading ECC
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* Copy Multiple times to sync DMA with Flash Controller
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*/
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ecc_ctrl = 0x5 |
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DMAC_CHAN_SRC_BURST_1 |
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DMAC_CHAN_DEST_BURST_1 |
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DMAC_CHAN_SRC_WIDTH_32 |
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DMAC_CHAN_DEST_WIDTH_32 |
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DMAC_CHAN_DEST_AHB1;
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/* CTRL descriptor entry for reading/writing Data */
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ctrl = (CONFIG_SYS_NAND_ECCSIZE / 4) |
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DMAC_CHAN_SRC_BURST_4 |
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DMAC_CHAN_DEST_BURST_4 |
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DMAC_CHAN_SRC_WIDTH_32 |
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DMAC_CHAN_DEST_WIDTH_32 |
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DMAC_CHAN_DEST_AHB1;
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/* CTRL descriptor entry for reading/writing Spare Area */
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oob_ctrl = (CONFIG_SYS_NAND_OOBSIZE / 4) |
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DMAC_CHAN_SRC_BURST_4 |
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DMAC_CHAN_DEST_BURST_4 |
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DMAC_CHAN_SRC_WIDTH_32 |
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DMAC_CHAN_DEST_WIDTH_32 |
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DMAC_CHAN_DEST_AHB1;
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if (read) {
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dmasrc = lpc32xx_dmac_set_dma_data();
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dmadst = (u32)buffer;
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ctrl |= DMAC_CHAN_DEST_AUTOINC;
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} else {
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dmadst = lpc32xx_dmac_set_dma_data();
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dmasrc = (u32)buffer;
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ctrl |= DMAC_CHAN_SRC_AUTOINC;
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}
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/*
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* Write Operation Sequence for Small Block NAND
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* ----------------------------------------------------------
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* 1. X'fer 256 bytes of data from Memory to Flash.
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* 2. Copy generated ECC data from Register to Spare Area
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* 3. X'fer next 256 bytes of data from Memory to Flash.
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* 4. Copy generated ECC data from Register to Spare Area.
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* 5. X'fer 16 byets of Spare area from Memory to Flash.
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* Read Operation Sequence for Small Block NAND
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* ----------------------------------------------------------
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* 1. X'fer 256 bytes of data from Flash to Memory.
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* 2. Copy generated ECC data from Register to ECC calc Buffer.
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* 3. X'fer next 256 bytes of data from Flash to Memory.
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* 4. Copy generated ECC data from Register to ECC calc Buffer.
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* 5. X'fer 16 bytes of Spare area from Flash to Memory.
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* Write Operation Sequence for Large Block NAND
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* ----------------------------------------------------------
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* 1. Steps(1-4) of Write Operations repeate for four times
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* which generates 16 DMA descriptors to X'fer 2048 bytes of
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* data & 32 bytes of ECC data.
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* 2. X'fer 64 bytes of Spare area from Memory to Flash.
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* Read Operation Sequence for Large Block NAND
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* ----------------------------------------------------------
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* 1. Steps(1-4) of Read Operations repeate for four times
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* which generates 16 DMA descriptors to X'fer 2048 bytes of
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* data & 32 bytes of ECC data.
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* 2. X'fer 64 bytes of Spare area from Flash to Memory.
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*/
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for (i = 0; i < size/CONFIG_SYS_NAND_ECCSIZE; i++) {
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dmalist_cur = &dmalist[i * 2];
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dmalist_cur_ecc = &dmalist[(i * 2) + 1];
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dmalist_cur->dma_src = (read ? (dmasrc) : (dmasrc + (i*256)));
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dmalist_cur->dma_dest = (read ? (dmadst + (i*256)) : dmadst);
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dmalist_cur->next_lli = lpc32xx_dmac_next_lli(dmalist_cur_ecc);
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dmalist_cur->next_ctrl = ctrl;
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dmalist_cur_ecc->dma_src = lpc32xx_dmac_set_ecc();
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dmalist_cur_ecc->dma_dest = (u32)&ecc_buffer[i];
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dmalist_cur_ecc->next_lli =
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lpc32xx_dmac_next_lli(&dmalist[(i * 2) + 2]);
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dmalist_cur_ecc->next_ctrl = ecc_ctrl;
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}
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if (i) { /* Data only transfer */
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dmalist_cur_ecc = &dmalist[(i * 2) - 1];
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dmalist_cur_ecc->next_lli = 0;
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dmalist_cur_ecc->next_ctrl |= DMAC_CHAN_INT_TC_EN;
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return;
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}
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/* OOB only transfer */
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if (read) {
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dmasrc = lpc32xx_dmac_set_dma_data();
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dmadst = (u32)buffer;
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oob_ctrl |= DMAC_CHAN_DEST_AUTOINC;
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} else {
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dmadst = lpc32xx_dmac_set_dma_data();
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dmasrc = (u32)buffer;
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oob_ctrl |= DMAC_CHAN_SRC_AUTOINC;
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}
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/* Read/ Write Spare Area Data To/From Flash */
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dmalist_cur = &dmalist[i * 2];
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dmalist_cur->dma_src = dmasrc;
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dmalist_cur->dma_dest = dmadst;
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dmalist_cur->next_lli = 0;
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dmalist_cur->next_ctrl = (oob_ctrl | DMAC_CHAN_INT_TC_EN);
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}
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static void lpc32xx_nand_xfer(struct mtd_info *mtd, const u8 *buf,
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int len, int read)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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u32 config;
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int ret;
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/* DMA Channel Configuration */
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config = (read ? DMAC_CHAN_FLOW_D_P2M : DMAC_CHAN_FLOW_D_M2P) |
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(read ? DMAC_DEST_PERIP(0) : DMAC_DEST_PERIP(DMA_PERID_NAND1)) |
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(read ? DMAC_SRC_PERIP(DMA_PERID_NAND1) : DMAC_SRC_PERIP(0)) |
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DMAC_CHAN_ENABLE;
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/* Prepare DMA descriptors */
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lpc32xx_nand_dma_configure(chip, buf, len, read);
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/* Setup SLC controller and start transfer */
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if (read)
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setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
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else /* NAND_ECC_WRITE */
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clrbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_DIR);
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setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_DMA_BURST);
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/* Write length for new transfers */
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if (!((readl(&lpc32xx_nand_slc_regs->stat) & STAT_DMA_FIFO) |
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readl(&lpc32xx_nand_slc_regs->tc))) {
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int tmp = (len != mtd->oobsize) ? mtd->oobsize : 0;
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writel(len + tmp, &lpc32xx_nand_slc_regs->tc);
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}
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setbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
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/* Start DMA transfers */
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ret = lpc32xx_dma_start_xfer(dmachan, dmalist, config);
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if (unlikely(ret < 0))
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BUG();
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/* Wait for NAND to be ready */
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while (!lpc32xx_nand_dev_ready(mtd))
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;
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/* Wait till DMA transfer is DONE */
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if (lpc32xx_dma_wait_status(dmachan))
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pr_err("NAND DMA transfer error!\r\n");
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/* Stop DMA & HW ECC */
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clrbits_le32(&lpc32xx_nand_slc_regs->ctrl, CTRL_DMA_START);
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clrbits_le32(&lpc32xx_nand_slc_regs->cfg,
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CFG_DMA_DIR | CFG_DMA_BURST | CFG_ECC_EN | CFG_DMA_ECC);
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}
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static u32 slc_ecc_copy_to_buffer(u8 *spare, const u32 *ecc, int count)
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{
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int i;
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for (i = 0; i < (count * CONFIG_SYS_NAND_ECCBYTES);
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i += CONFIG_SYS_NAND_ECCBYTES) {
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u32 ce = ecc[i / CONFIG_SYS_NAND_ECCBYTES];
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ce = ~(ce << 2) & 0xFFFFFF;
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spare[i+2] = (u8)(ce & 0xFF); ce >>= 8;
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spare[i+1] = (u8)(ce & 0xFF); ce >>= 8;
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spare[i] = (u8)(ce & 0xFF);
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}
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return 0;
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}
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static int lpc32xx_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
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uint8_t *ecc_code)
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{
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return slc_ecc_copy_to_buffer(ecc_code, ecc_buffer, ECCSTEPS);
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}
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/*
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* Enables and prepares SLC NAND controller
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* for doing data transfers with H/W ECC enabled.
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*/
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static void lpc32xx_hwecc_enable(struct mtd_info *mtd, int mode)
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{
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/* Clear ECC */
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writel(CTRL_ECC_CLEAR, &lpc32xx_nand_slc_regs->ctrl);
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/* Setup SLC controller for H/W ECC operations */
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setbits_le32(&lpc32xx_nand_slc_regs->cfg, CFG_ECC_EN | CFG_DMA_ECC);
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}
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/*
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* lpc32xx_correct_data - [NAND Interface] Detect and correct bit error(s)
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* mtd: MTD block structure
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* dat: raw data read from the chip
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* read_ecc: ECC from the chip
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* calc_ecc: the ECC calculated from raw data
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*
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* Detect and correct a 1 bit error for 256 byte block
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*/
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int lpc32xx_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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unsigned int i;
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int ret1, ret2 = 0;
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u_char *r = read_ecc;
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u_char *c = calc_ecc;
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u16 data_offset = 0;
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for (i = 0 ; i < ECCSTEPS ; i++) {
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r += CONFIG_SYS_NAND_ECCBYTES;
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c += CONFIG_SYS_NAND_ECCBYTES;
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data_offset += CONFIG_SYS_NAND_ECCSIZE;
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ret1 = nand_correct_data(mtd, dat + data_offset, r, c);
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if (ret1 < 0)
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return -EBADMSG;
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else
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ret2 += ret1;
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}
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return ret2;
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}
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#endif
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#if defined(CONFIG_DMA_LPC32XX)
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static void lpc32xx_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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lpc32xx_nand_xfer(mtd, buf, len, 1);
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}
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#else
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static void lpc32xx_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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while (len-- > 0)
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*buf++ = readl(&lpc32xx_nand_slc_regs->data);
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}
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#endif
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static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
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{
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return readl(&lpc32xx_nand_slc_regs->data);
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}
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#if defined(CONFIG_DMA_LPC32XX)
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static void lpc32xx_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf,
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int len)
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{
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lpc32xx_nand_xfer(mtd, buf, len, 0);
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}
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#else
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static void lpc32xx_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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while (len-- > 0)
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writel(*buf++, &lpc32xx_nand_slc_regs->data);
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}
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#endif
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static void lpc32xx_write_byte(struct mtd_info *mtd, uint8_t byte)
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{
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writel(byte, &lpc32xx_nand_slc_regs->data);
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}
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#if defined(CONFIG_DMA_LPC32XX)
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/* Reuse the logic from "nand_read_page_hwecc()" */
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static int lpc32xx_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
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uint8_t *buf, int oob_required, int page)
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{
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int i;
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int stat;
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uint8_t *p = buf;
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uint8_t *ecc_calc = chip->buffers->ecccalc;
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uint8_t *ecc_code = chip->buffers->ecccode;
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uint32_t *eccpos = chip->ecc.layout->eccpos;
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unsigned int max_bitflips = 0;
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|
|
|
/*
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* As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
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* and section 9.7, the NAND SLC & DMA allowed single DMA transaction
|
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* of a page size using DMA controller scatter/gather mode through
|
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* linked list; the ECC read is done without any software intervention.
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*/
|
|
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lpc32xx_hwecc_enable(mtd, NAND_ECC_READ);
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lpc32xx_dma_read_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
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lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
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lpc32xx_dma_read_buf(mtd, chip->oob_poi, mtd->oobsize);
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|
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for (i = 0; i < chip->ecc.total; i++)
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ecc_code[i] = chip->oob_poi[eccpos[i]];
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stat = chip->ecc.correct(mtd, p, &ecc_code[0], &ecc_calc[0]);
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if (stat < 0)
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mtd->ecc_stats.failed++;
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else {
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mtd->ecc_stats.corrected += stat;
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max_bitflips = max_t(unsigned int, max_bitflips, stat);
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}
|
|
|
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return max_bitflips;
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}
|
|
|
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/* Reuse the logic from "nand_write_page_hwecc()" */
|
|
static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
|
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struct nand_chip *chip,
|
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const uint8_t *buf, int oob_required,
|
|
int page)
|
|
{
|
|
int i;
|
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uint8_t *ecc_calc = chip->buffers->ecccalc;
|
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const uint8_t *p = buf;
|
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uint32_t *eccpos = chip->ecc.layout->eccpos;
|
|
|
|
/*
|
|
* As per the "LPC32x0 and LPC32x0/01 User manual" table 173 notes
|
|
* and section 9.7, the NAND SLC & DMA allowed single DMA transaction
|
|
* of a page size using DMA controller scatter/gather mode through
|
|
* linked list; the ECC read is done without any software intervention.
|
|
*/
|
|
|
|
lpc32xx_hwecc_enable(mtd, NAND_ECC_WRITE);
|
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lpc32xx_dma_write_buf(mtd, p, chip->ecc.size * chip->ecc.steps);
|
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lpc32xx_ecc_calculate(mtd, p, &ecc_calc[0]);
|
|
|
|
for (i = 0; i < chip->ecc.total; i++)
|
|
chip->oob_poi[eccpos[i]] = ecc_calc[i];
|
|
|
|
lpc32xx_dma_write_buf(mtd, chip->oob_poi, mtd->oobsize);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* LPC32xx has only one SLC NAND controller, don't utilize
|
|
* CONFIG_SYS_NAND_SELF_INIT to be able to reuse this function
|
|
* both in SPL NAND and U-Boot images.
|
|
*/
|
|
int board_nand_init(struct nand_chip *lpc32xx_chip)
|
|
{
|
|
#if defined(CONFIG_DMA_LPC32XX)
|
|
int ret;
|
|
|
|
/* Acquire a channel for our use */
|
|
ret = lpc32xx_dma_get_channel();
|
|
if (unlikely(ret < 0)) {
|
|
pr_info("Unable to get free DMA channel for NAND transfers\n");
|
|
return -1;
|
|
}
|
|
dmachan = (unsigned int)ret;
|
|
#endif
|
|
|
|
lpc32xx_chip->cmd_ctrl = lpc32xx_nand_cmd_ctrl;
|
|
lpc32xx_chip->dev_ready = lpc32xx_nand_dev_ready;
|
|
|
|
/*
|
|
* The implementation of these functions is quite common, but
|
|
* they MUST be defined, because access to data register
|
|
* is strictly 32-bit aligned.
|
|
*/
|
|
lpc32xx_chip->read_byte = lpc32xx_read_byte;
|
|
lpc32xx_chip->write_byte = lpc32xx_write_byte;
|
|
|
|
#if defined(CONFIG_DMA_LPC32XX)
|
|
/* Hardware ECC calculation is supported when DMA driver is selected */
|
|
lpc32xx_chip->ecc.mode = NAND_ECC_HW;
|
|
|
|
lpc32xx_chip->read_buf = lpc32xx_dma_read_buf;
|
|
lpc32xx_chip->write_buf = lpc32xx_dma_write_buf;
|
|
|
|
lpc32xx_chip->ecc.calculate = lpc32xx_ecc_calculate;
|
|
lpc32xx_chip->ecc.correct = lpc32xx_correct_data;
|
|
lpc32xx_chip->ecc.hwctl = lpc32xx_hwecc_enable;
|
|
lpc32xx_chip->chip_delay = 2000;
|
|
|
|
lpc32xx_chip->ecc.read_page = lpc32xx_read_page_hwecc;
|
|
lpc32xx_chip->ecc.write_page = lpc32xx_write_page_hwecc;
|
|
lpc32xx_chip->options |= NAND_NO_SUBPAGE_WRITE;
|
|
#else
|
|
/*
|
|
* Hardware ECC calculation is not supported by the driver,
|
|
* because it requires DMA support, see LPC32x0 User Manual,
|
|
* note after SLC_ECC register description (UM10326, p.198)
|
|
*/
|
|
lpc32xx_chip->ecc.mode = NAND_ECC_SOFT;
|
|
|
|
/*
|
|
* The implementation of these functions is quite common, but
|
|
* they MUST be defined, because access to data register
|
|
* is strictly 32-bit aligned.
|
|
*/
|
|
lpc32xx_chip->read_buf = lpc32xx_read_buf;
|
|
lpc32xx_chip->write_buf = lpc32xx_write_buf;
|
|
#endif
|
|
|
|
/*
|
|
* These values are predefined
|
|
* for both small and large page NAND flash devices.
|
|
*/
|
|
lpc32xx_chip->ecc.size = CONFIG_SYS_NAND_ECCSIZE;
|
|
lpc32xx_chip->ecc.bytes = CONFIG_SYS_NAND_ECCBYTES;
|
|
lpc32xx_chip->ecc.strength = 1;
|
|
|
|
if (CONFIG_SYS_NAND_PAGE_SIZE != NAND_LARGE_BLOCK_PAGE_SIZE)
|
|
lpc32xx_chip->ecc.layout = &lpc32xx_nand_oob_16;
|
|
|
|
#if defined(CONFIG_SYS_NAND_USE_FLASH_BBT)
|
|
lpc32xx_chip->bbt_options |= NAND_BBT_USE_FLASH;
|
|
#endif
|
|
|
|
/* Initialize NAND interface */
|
|
lpc32xx_nand_init();
|
|
|
|
return 0;
|
|
}
|
|
|