upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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149 lines
3.6 KiB
149 lines
3.6 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* Yoo. Jonghoon, IPone, yooth@ipone.co.kr
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* U-Boot port on RPXlite board
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*
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* DRAM related UPMA register values are modified.
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* See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS
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*/
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#include <common.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFCC25
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 00h in UPMA RAM)
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*/
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0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08,
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0x3FBFCC27, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Read. (Offset 08h in UPMA RAM)
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*/
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0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88,
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0x3FBFCC27, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18h in UPMA RAM)
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*/
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0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00,
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0x3FFFCC27, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20h in UPMA RAM)
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*/
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0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C,
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0x0CFFCC00, 0x33FFCC27, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_,
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/*
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* Refresh. (Offset 30h in UPMA RAM)
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*/
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0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24,
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0x3FFFCC27, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3Ch in UPMA RAM)
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*/
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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puts ("Board: RPXlite\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size10;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/* Refresh clock prescalar */
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memctl->memc_mptpr = CONFIG_SYS_MPTPR;
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memctl->memc_mar = 0x00000000;
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/* Map controller banks 1 to the SDRAM bank */
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memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
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memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
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memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */
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udelay (1);
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/* Check Bank 0 Memory Size
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* try 10 column mode
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*/
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size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
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SDRAM_MAX_SIZE);
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return (size10);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size (base, maxsize));
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}
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