upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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411 lines
9.6 KiB
411 lines
9.6 KiB
/*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same I2C controller inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#ifdef CONFIG_DRIVER_S3C24X0_I2C
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#if defined(CONFIG_S3C2400)
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#include <s3c2400.h>
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#elif defined(CONFIG_S3C2410)
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#include <s3c2410.h>
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#endif
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#include <i2c.h>
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#ifdef CONFIG_HARD_I2C
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#define IIC_WRITE 0
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#define IIC_READ 1
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#define IIC_OK 0
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#define IIC_NOK 1
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#define IIC_NACK 2
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#define IIC_NOK_LA 3 /* Lost arbitration */
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#define IIC_NOK_TOUT 4 /* time out */
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#define IICSTAT_BSY 0x20 /* Busy bit */
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#define IICSTAT_NACK 0x01 /* Nack bit */
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#define IICCON_IRPND 0x10 /* Interrupt pending bit */
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#define IIC_MODE_MT 0xC0 /* Master Transmit Mode */
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#define IIC_MODE_MR 0x80 /* Master Receive Mode */
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#define IIC_START_STOP 0x20 /* START / STOP */
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#define IIC_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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#define IIC_TIMEOUT 1 /* 1 seconde */
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static int GetIICSDA(void)
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{
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return (rGPEDAT & 0x8000) >> 15;
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}
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#if 0
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static void SetIICSDA(int x)
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{
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rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
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}
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#endif
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static void SetIICSCL(int x)
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{
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rGPEDAT = (rGPEDAT & ~0x4000) | (x&1) << 14;
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}
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static int WaitForXfer(void)
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{
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int i, status;
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i = IIC_TIMEOUT * 1000;
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status = rIICCON;
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while ((i > 0) && !(status & IICCON_IRPND)) {
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udelay(1000);
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status = rIICCON;
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i--;
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}
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return(status & IICCON_IRPND) ? IIC_OK : IIC_NOK_TOUT;
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}
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static int IsACK(void)
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{
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return(!(rIICSTAT & IICSTAT_NACK));
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}
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static void ReadWriteByte(void)
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{
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rIICCON &= ~IICCON_IRPND;
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}
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void i2c_init (int speed, int slaveadd)
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{
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ulong freq, pres = 16, div;
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int i, status;
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/* wait for some time to give previous transfer a chance to finish */
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i = IIC_TIMEOUT * 1000;
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status = rIICSTAT;
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while ((i > 0) && (status & IICSTAT_BSY)) {
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udelay(1000);
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status = rIICSTAT;
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i--;
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}
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if ((status & IICSTAT_BSY) || GetIICSDA() == 0) {
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ulong old_gpecon = rGPECON;
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/* bus still busy probably by (most) previously interrupted transfer */
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/* set IICSDA and IICSCL (GPE15, GPE14) to GPIO */
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rGPECON = (rGPECON & ~0xF0000000) | 0x10000000;
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/* toggle IICSCL until bus idle */
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SetIICSCL(0); udelay(1000);
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i = 10;
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while ((i > 0) && (GetIICSDA() != 1)) {
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SetIICSCL(1); udelay(1000);
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SetIICSCL(0); udelay(1000);
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i--;
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}
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SetIICSCL(1); udelay(1000);
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/* restore pin functions */
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rGPECON = old_gpecon;
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}
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/* calculate prescaler and divisor values */
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freq = get_PCLK();
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if ((freq / pres / (16+1)) > speed)
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/* set prescaler to 512 */
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pres = 512;
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div = 0;
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while ((freq / pres / (div+1)) > speed)
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div++;
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/* set prescaler, divisor according to freq, also set
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ACKGEN, IRQ */
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rIICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
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/* init to SLAVE REVEIVE and set slaveaddr */
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rIICSTAT = 0;
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rIICADD = slaveadd;
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/* program Master Transmit (and implicit STOP) */
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rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
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}
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/*
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cmd_type is 0 for write 1 for read.
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addr_len can take any value from 0-255, it is only limited
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by the char, we could make it larger if needed. If it is
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0 we skip the address write cycle.
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*/
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static
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int i2c_transfer(unsigned char cmd_type,
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unsigned char chip,
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unsigned char addr[],
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unsigned char addr_len,
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unsigned char data[],
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unsigned short data_len)
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{
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int i, status, result;
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if (data == 0 || data_len == 0) {
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/*Don't support data transfer of no length or to address 0*/
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printf( "i2c_transfer: bad call\n" );
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return IIC_NOK;
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}
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//CheckDelay();
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/* Check I2C bus idle */
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i = IIC_TIMEOUT * 1000;
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status = rIICSTAT;
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while ((i > 0) && (status & IICSTAT_BSY)) {
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udelay(1000);
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status = rIICSTAT;
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i--;
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}
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if (status & IICSTAT_BSY) {
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result = IIC_NOK_TOUT;
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return(result);
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}
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rIICCON |= 0x80;
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result = IIC_OK;
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switch (cmd_type) {
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case IIC_WRITE:
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if (addr && addr_len) {
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rIICDS = chip;
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/* send START */
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rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
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i = 0;
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while ((i < addr_len) && (result == IIC_OK)) {
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result = WaitForXfer();
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rIICDS = addr[i];
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ReadWriteByte();
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i++;
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}
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i = 0;
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while ((i < data_len) && (result == IIC_OK)) {
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result = WaitForXfer();
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rIICDS = data[i];
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ReadWriteByte();
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i++;
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}
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} else {
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rIICDS = chip;
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/* send START */
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rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA | IIC_START_STOP;
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i = 0;
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while ((i < data_len) && (result = IIC_OK)) {
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result = WaitForXfer();
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rIICDS = data[i];
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ReadWriteByte();
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i++;
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}
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}
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if (result == IIC_OK)
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result = WaitForXfer();
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/* send STOP */
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rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
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ReadWriteByte();
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break;
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case IIC_READ:
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if (addr && addr_len) {
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rIICSTAT = IIC_MODE_MT | IIC_TXRX_ENA;
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rIICDS = chip;
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/* send START */
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rIICSTAT |= IIC_START_STOP;
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result = WaitForXfer();
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if (IsACK()) {
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i = 0;
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while ((i < addr_len) && (result == IIC_OK)) {
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rIICDS = addr[i];
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ReadWriteByte();
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result = WaitForXfer();
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i++;
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}
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rIICDS = chip;
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/* resend START */
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rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA | IIC_START_STOP;
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ReadWriteByte();
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result = WaitForXfer();
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i = 0;
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while ((i < data_len) && (result == IIC_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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rIICCON &= ~0x80;
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ReadWriteByte();
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result = WaitForXfer();
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data[i] = rIICDS;
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i++;
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}
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} else {
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result = IIC_NACK;
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}
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} else {
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rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
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rIICDS = chip;
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/* send START */
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rIICSTAT |= IIC_START_STOP;
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result = WaitForXfer();
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if (IsACK()) {
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i = 0;
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while ((i < data_len) && (result == IIC_OK)) {
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/* disable ACK for final READ */
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if (i == data_len - 1)
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rIICCON &= ~0x80;
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ReadWriteByte();
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result = WaitForXfer();
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data[i] = rIICDS;
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i++;
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}
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} else {
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result = IIC_NACK;
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}
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}
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/* send STOP */
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rIICSTAT = IIC_MODE_MR | IIC_TXRX_ENA;
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ReadWriteByte();
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break;
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default:
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printf( "i2c_transfer: bad call\n" );
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result = IIC_NOK;
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break;
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}
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return (result);
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}
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int i2c_probe (uchar chip)
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{
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uchar buf[1];
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buf[0] = 0;
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/*
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* What is needed is to send the chip address and verify that the
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* address was <ACK>ed (i.e. there was a chip at that address which
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* drove the data line low).
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*/
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return(i2c_transfer (IIC_READ, chip << 1, 0, 0, buf, 1) != IIC_OK);
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}
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int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
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{
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uchar xaddr[4];
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int ret;
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if ( alen > 4 ) {
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printf ("I2C read: addr len %d not supported\n", alen);
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return 1;
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}
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if ( alen > 0 ) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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}
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#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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if( alen > 0 )
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chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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if( (ret = i2c_transfer(IIC_READ, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
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printf( "I2c read: failed %d\n", ret);
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return 1;
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}
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return 0;
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}
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int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
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{
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uchar xaddr[4];
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if ( alen > 4 ) {
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printf ("I2C write: addr len %d not supported\n", alen);
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return 1;
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}
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if ( alen > 0 ) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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}
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#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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if( alen > 0 )
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chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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return (i2c_transfer(IIC_WRITE, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
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}
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#endif /* CONFIG_HARD_I2C */
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#endif /* CONFIG_DRIVER_S3C24X0_I2C */
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