upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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532 lines
11 KiB
532 lines
11 KiB
/*
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* (C) Copyright 2010,2011
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* Graeme Russ, <graeme.russ@gmail.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/processor-flags.h>
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#include <asm/ic/sc520.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sc520_sdram_info {
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u8 banks;
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u8 columns;
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u8 rows;
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u8 size;
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};
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static void sc520_sizemem(void);
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static void sc520_set_dram_timing(void);
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static void sc520_set_dram_refresh_rate(void);
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static void sc520_enable_dram_refresh(void);
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static void sc520_enable_sdram(void);
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#if CONFIG_SYS_SDRAM_ECC_ENABLE
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static void sc520_enable_ecc(void)
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#endif
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int dram_init_f(void)
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{
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sc520_sizemem();
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sc520_set_dram_timing();
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sc520_set_dram_refresh_rate();
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sc520_enable_dram_refresh();
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sc520_enable_sdram();
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#if CONFIG_SYS_SDRAM_ECC_ENABLE
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sc520_enable_ecc();
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#endif
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return 0;
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}
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static inline void sc520_dummy_write(void)
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{
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writew(0x0000, CACHELINESZ);
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}
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static inline void sc520_issue_sdram_op_mode_select(u8 command)
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{
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writeb(command, &sc520_mmcr->drcctl);
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sc520_dummy_write();
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}
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static inline int check_long(u32 test_long)
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{
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u8 i;
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u8 tmp_byte = (u8)(test_long & 0x000000ff);
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for (i = 1; i < 4; i++) {
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if ((u8)((test_long >> (i * 8)) & 0x000000ff) != tmp_byte)
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return -1;
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}
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return 0;
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}
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static inline int write_and_test(u32 data, u32 address)
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{
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writel(data, address);
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if (readl(address) == data)
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return 0; /* Good */
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else
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return -1; /* Bad */
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}
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static void sc520_enable_sdram(void)
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{
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u32 par_config;
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/* Enable Writes, Caching and Code Execution to SDRAM */
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par_config = readl(&sc520_mmcr->par[3]);
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par_config &= ~(SC520_PAR_EXEC_DIS |
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SC520_PAR_CACHE_DIS |
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SC520_PAR_WRITE_DIS);
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writel(par_config, &sc520_mmcr->par[3]);
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par_config = readl(&sc520_mmcr->par[4]);
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par_config &= ~(SC520_PAR_EXEC_DIS |
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SC520_PAR_CACHE_DIS |
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SC520_PAR_WRITE_DIS);
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writel(par_config, &sc520_mmcr->par[4]);
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}
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static void sc520_set_dram_timing(void)
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{
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u8 drctmctl = 0x00;
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#if defined CONFIG_SYS_SDRAM_DRCTMCTL
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/* just have your hardware designer _GIVE_ you what you need here! */
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drctmctl = CONFIG_SYS_SDRAM_DRCTMCTL;
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#else
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switch (CONFIG_SYS_SDRAM_RAS_CAS_DELAY) {
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case 2:
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break;
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case 3:
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drctmctl |= 0x01;
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break;
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case 4:
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default:
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drctmctl |= 0x02;
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break;
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}
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switch (CONFIG_SYS_SDRAM_PRECHARGE_DELAY) {
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case 2:
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break;
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case 3:
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drctmctl |= 0x04;
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break;
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case 4:
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default:
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drctmctl |= 0x08;
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break;
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case 6:
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drctmctl |= 0x0c;
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break;
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}
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switch (CONFIG_SYS_SDRAM_CAS_LATENCY) {
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case 2:
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break;
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case 3:
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default:
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drctmctl |= 0x10;
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break;
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}
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#endif
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writeb(drctmctl, &sc520_mmcr->drctmctl);
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/* Issue load mode register command */
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sc520_issue_sdram_op_mode_select(0x03);
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}
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static void sc520_set_dram_refresh_rate(void)
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{
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u8 drctl;
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drctl = readb(&sc520_mmcr->drcctl);
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drctl &= 0xcf;
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switch (CONFIG_SYS_SDRAM_REFRESH_RATE) {
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case 78:
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break;
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case 156:
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default:
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drctl |= 0x10;
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break;
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case 312:
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drctl |= 0x20;
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break;
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case 624:
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drctl |= 0x30;
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break;
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}
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writeb(drctl, &sc520_mmcr->drcctl);
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}
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static void sc520_enable_dram_refresh(void)
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{
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u8 drctl;
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drctl = readb(&sc520_mmcr->drcctl);
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drctl &= 0x30; /* keep refresh rate */
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drctl |= 0x08; /* enable refresh, normal mode */
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writeb(drctl, &sc520_mmcr->drcctl);
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}
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static void sc520_get_bank_info(int bank, struct sc520_sdram_info *bank_info)
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{
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u32 col_data;
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u32 row_data;
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u32 drcbendadr;
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u16 drccfg;
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u8 banks = 0x00;
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u8 columns = 0x00;
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u8 rows = 0x00;
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bank_info->banks = 0x00;
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bank_info->columns = 0x00;
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bank_info->rows = 0x00;
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bank_info->size = 0x00;
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if ((bank < 0) || (bank > 3)) {
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printf("Bad Bank ID\n");
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return;
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}
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/* Save configuration */
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drcbendadr = readl(&sc520_mmcr->drcbendadr);
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drccfg = readw(&sc520_mmcr->drccfg);
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/* Setup SDRAM Bank to largest possible size */
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writew(0x000b << (bank * 4), &sc520_mmcr->drccfg);
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/* Set ending address for this bank */
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writel(0x000000ff << (bank * 8), &sc520_mmcr->drcbendadr);
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/* write col 11 wrap adr */
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if (write_and_test(COL11_DATA, COL11_ADR) != 0)
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goto restore_and_exit;
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/* write col 10 wrap adr */
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if (write_and_test(COL10_DATA, COL10_ADR) != 0)
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goto restore_and_exit;
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/* write col 9 wrap adr */
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if (write_and_test(COL09_DATA, COL09_ADR) != 0)
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goto restore_and_exit;
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/* write col 8 wrap adr */
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if (write_and_test(COL08_DATA, COL08_ADR) != 0)
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goto restore_and_exit;
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col_data = readl(COL11_ADR);
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/* All four bytes in the read long must be the same */
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if (check_long(col_data) < 0)
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goto restore_and_exit;
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if ((col_data >= COL08_DATA) && (col_data <= COL11_DATA))
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columns = (u8)(col_data & 0x000000ff);
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else
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goto restore_and_exit;
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/* write row 14 wrap adr */
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if (write_and_test(ROW14_DATA, ROW14_ADR) != 0)
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goto restore_and_exit;
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/* write row 13 wrap adr */
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if (write_and_test(ROW13_DATA, ROW13_ADR) != 0)
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goto restore_and_exit;
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/* write row 12 wrap adr */
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if (write_and_test(ROW12_DATA, ROW12_ADR) != 0)
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goto restore_and_exit;
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/* write row 11 wrap adr */
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if (write_and_test(ROW11_DATA, ROW11_ADR) != 0)
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goto restore_and_exit;
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if (write_and_test(ROW10_DATA, ROW10_ADR) != 0)
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goto restore_and_exit;
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/*
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* read data @ row 12 wrap adr to determine number of banks,
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* and read data @ row 14 wrap adr to determine number of rows.
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* if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
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* if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
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* if data @ row 12 wrap == 11 or 12, we have 4 banks,
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*/
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row_data = readl(ROW12_ADR);
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/* All four bytes in the read long must be the same */
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if (check_long(row_data) != 0)
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goto restore_and_exit;
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switch (row_data) {
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case ROW10_DATA:
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banks = 2;
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break;
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case ROW11_DATA:
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case ROW12_DATA:
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banks = 4;
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break;
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default:
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goto restore_and_exit;
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}
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row_data = readl(ROW14_ADR);
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/* All four bytes in the read long must be the same */
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if (check_long(row_data) != 0)
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goto restore_and_exit;
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switch (row_data) {
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case ROW11_DATA:
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case ROW12_DATA:
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case ROW13_DATA:
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case ROW14_DATA:
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rows = (u8)(row_data & 0x000000ff);
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break;
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default:
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goto restore_and_exit;
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}
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bank_info->banks = banks;
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bank_info->columns = columns;
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bank_info->rows = rows;
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if ((bank_info->banks != 0) &&
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(bank_info->columns != 0) &&
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(bank_info->rows != 0)) {
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bank_info->size = bank_info->rows;
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bank_info->size >>= (11 - bank_info->columns);
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bank_info->size++;
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}
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restore_and_exit:
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/* Restore configuration */
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writel(drcbendadr, &sc520_mmcr->drcbendadr);
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writew(drccfg, &sc520_mmcr->drccfg);
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}
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static void sc520_setup_sizemem(void)
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{
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u8 i;
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/* Disable write buffer */
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writeb(0x00, &sc520_mmcr->dbctl);
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/* Disable ECC */
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writeb(0x00, &sc520_mmcr->eccctl);
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/* Set slowest SDRAM timing */
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writeb(0x1e, &sc520_mmcr->drctmctl);
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/* Issue a NOP to all SDRAM banks */
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sc520_issue_sdram_op_mode_select(0x01);
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/* Delay for 100 microseconds */
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udelay(100);
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/* Issue 'All Banks Precharge' command */
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sc520_issue_sdram_op_mode_select(0x02);
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/* Issue 2 'Auto Refresh Enable' command */
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sc520_issue_sdram_op_mode_select(0x04);
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sc520_dummy_write();
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/* Issue 'Load Mode Register' command */
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sc520_issue_sdram_op_mode_select(0x03);
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/* Issue 8 more 'Auto Refresh Enable' commands */
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sc520_issue_sdram_op_mode_select(0x04);
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for (i = 0; i < 7; i++)
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sc520_dummy_write();
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/* Set control register to 'Normal Mode' */
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writeb(0x00, &sc520_mmcr->drcctl);
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}
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static void sc520_sizemem(void)
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{
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struct sc520_sdram_info sdram_info[4];
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u8 bank_config = 0x00;
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u8 end_addr = 0x00;
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u16 drccfg = 0x0000;
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u32 drcbendadr = 0x00000000;
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u8 i;
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/* Use PARs to disable caching of maximum allowable 256MB SDRAM */
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writel(SC520_SDRAM1_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[3]);
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writel(SC520_SDRAM2_PAR | SC520_PAR_CACHE_DIS, &sc520_mmcr->par[4]);
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sc520_setup_sizemem();
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gd->ram_size = 0;
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/* Size each SDRAM bank */
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for (i = 0; i <= 3; i++) {
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sc520_get_bank_info(i, &sdram_info[i]);
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if (sdram_info[i].banks != 0) {
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/* Update Configuration register */
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bank_config = sdram_info[i].columns - 8;
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if (sdram_info[i].banks == 4)
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bank_config |= 0x08;
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drccfg |= bank_config << (i * 4);
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/* Update End Address register */
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end_addr += sdram_info[i].size;
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drcbendadr |= (end_addr | 0x80) << (i * 8);
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gd->ram_size += sdram_info[i].size << 22;
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}
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/* Issue 'All Banks Precharge' command */
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sc520_issue_sdram_op_mode_select(0x02);
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/* Set control register to 'Normal Mode' */
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writeb(0x00, &sc520_mmcr->drcctl);
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}
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writel(drcbendadr, &sc520_mmcr->drcbendadr);
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writew(drccfg, &sc520_mmcr->drccfg);
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/* Clear PARs preventing caching of SDRAM */
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writel(0x00000000, &sc520_mmcr->par[3]);
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writel(0x00000000, &sc520_mmcr->par[4]);
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}
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#if CONFIG_SYS_SDRAM_ECC_ENABLE
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static void sc520_enable_ecc(void)
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/* A nominal memory test: just a byte at each address line */
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movl %eax, %ecx
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shrl $0x1, %ecx
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movl $0x1, %edi
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memtest0:
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movb $0xa5, (%edi)
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cmpb $0xa5, (%edi)
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jne out
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shrl $0x1, %ecx
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andl %ecx, %ecx
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jz set_ecc
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shll $0x1, %edi
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jmp memtest0
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set_ecc:
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/* clear all ram with a memset */
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movl %eax, %ecx
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xorl %esi, %esi
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xorl %edi, %edi
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xorl %eax, %eax
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shrl $0x2, %ecx
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cld
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rep stosl
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/* enable read, write buffers */
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movb $0x11, %al
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movl $DBCTL, %edi
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movb %al, (%edi)
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/* enable NMI mapping for ECC */
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movl $ECCINT, %edi
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movb $0x10, %al
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movb %al, (%edi)
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/* Turn on ECC */
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movl $ECCCTL, %edi
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movb $0x05, %al
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movb %al,(%edi)
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out:
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jmp init_ecc_ret
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}
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#endif
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int dram_init(void)
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{
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ulong dram_ctrl;
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ulong dram_present = 0x00000000;
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/*
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* We read-back the configuration of the dram
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* controller that the assembly code wrote
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*/
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dram_ctrl = readl(&sc520_mmcr->drcbendadr);
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gd->bd->bi_dram[0].start = 0;
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if (dram_ctrl & 0x80) {
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/* bank 0 enabled */
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gd->bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
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dram_present = gd->bd->bi_dram[1].start;
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gd->bd->bi_dram[0].size = gd->bd->bi_dram[1].start;
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} else {
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gd->bd->bi_dram[0].size = 0;
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gd->bd->bi_dram[1].start = gd->bd->bi_dram[0].start;
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}
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if (dram_ctrl & 0x8000) {
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/* bank 1 enabled */
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gd->bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
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dram_present = gd->bd->bi_dram[2].start;
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gd->bd->bi_dram[1].size = gd->bd->bi_dram[2].start -
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gd->bd->bi_dram[1].start;
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} else {
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gd->bd->bi_dram[1].size = 0;
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gd->bd->bi_dram[2].start = gd->bd->bi_dram[1].start;
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}
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if (dram_ctrl & 0x800000) {
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/* bank 2 enabled */
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gd->bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
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dram_present = gd->bd->bi_dram[3].start;
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gd->bd->bi_dram[2].size = gd->bd->bi_dram[3].start -
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gd->bd->bi_dram[2].start;
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} else {
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gd->bd->bi_dram[2].size = 0;
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gd->bd->bi_dram[3].start = gd->bd->bi_dram[2].start;
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}
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if (dram_ctrl & 0x80000000) {
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/* bank 3 enabled */
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dram_present = (dram_ctrl & 0x7f000000) >> 2;
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|
gd->bd->bi_dram[3].size = dram_present -
|
|
gd->bd->bi_dram[3].start;
|
|
} else {
|
|
gd->bd->bi_dram[3].size = 0;
|
|
}
|
|
|
|
gd->ram_size = dram_present;
|
|
|
|
return 0;
|
|
}
|
|
|