upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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64 lines
1.5 KiB
64 lines
1.5 KiB
/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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if (ctrl_num) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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/* automatic calibration for nb of cycles between read and DQS pre */
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popts->cpo_override = 0xFF;
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/* 1/2 clk delay between wr command and data strobe */
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popts->write_data_delay = 4;
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/* clk lauched 1/2 applied cylcle after address command */
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popts->clk_adjust = 4;
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/* 1T timing: command/address held for only 1 cycle */
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popts->twot_en = 0;
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/* we have only one module, half str should be OK */
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popts->half_strength_driver_enable = 1;
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/* wrlvl values overriden as recommended by ddr init func */
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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popts->wrlvl_start = 0x6;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 75 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR_ODT_75ohm;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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puts("Initializing with SPD\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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debug(" DDR: ");
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return dram_size;
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}
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