upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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60 lines
1.1 KiB
60 lines
1.1 KiB
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/nios2.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
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extern void display_sysid (void);
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#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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printf ("CPU : Nios-II\n");
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#if !defined(CONFIG_SYS_NIOS_SYSID_BASE)
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printf ("SYSID : <unknown>\n");
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#else
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display_sysid ();
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#endif
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return (0);
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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/* indirect call to go beyond 256MB limitation of toolchain */
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nios2_callr(CONFIG_SYS_RESET_ADDR);
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return 0;
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}
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int dcache_status(void)
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{
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return 1;
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}
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void dcache_enable(void)
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{
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flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
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}
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void dcache_disable(void)
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{
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flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
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}
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int arch_cpu_init(void)
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{
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gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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