upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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304 lines
6.8 KiB
304 lines
6.8 KiB
#include <common.h>
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#if defined(CONFIG_8xx)
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#include <mpc8xx.h>
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#endif
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#include <pcmcia.h>
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#undef CONFIG_PCMCIA
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA)
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#define CONFIG_PCMCIA
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#endif
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#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || defined(CONFIG_CMD_IDE)) && defined(CONFIG_IDE_8xx_PCCARD)
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#define CONFIG_PCMCIA
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#endif
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#if defined(CONFIG_8xx) && defined(CONFIG_PCMCIA)
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#if defined(CONFIG_IDE_8xx_PCCARD)
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extern int check_ide_device (int slot);
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#endif
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extern int pcmcia_hardware_enable (int slot);
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extern int pcmcia_voltage_set(int slot, int vcc, int vpp);
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA)
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extern int pcmcia_hardware_disable(int slot);
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#endif
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static u_int m8xx_get_graycode(u_int size);
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#if 0 /* Disabled */
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static u_int m8xx_get_speed(u_int ns, u_int is_io);
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#endif
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/* look up table for pgcrx registers */
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u_int *pcmcia_pgcrx[2] = {
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&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcra,
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&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb,
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};
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/*
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* Search this table to see if the windowsize is
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* supported...
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*/
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#define M8XX_SIZES_NO 32
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static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] =
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{ 0x00000001, 0x00000002, 0x00000008, 0x00000004,
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0x00000080, 0x00000040, 0x00000010, 0x00000020,
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0x00008000, 0x00004000, 0x00001000, 0x00002000,
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0x00000100, 0x00000200, 0x00000800, 0x00000400,
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0x0fffffff, 0xffffffff, 0xffffffff, 0xffffffff,
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0x01000000, 0x02000000, 0xffffffff, 0x04000000,
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0x00010000, 0x00020000, 0x00080000, 0x00040000,
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0x00800000, 0x00400000, 0x00100000, 0x00200000 };
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/* -------------------------------------------------------------------- */
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#ifdef CONFIG_HMI10
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#define HMI10_FRAM_TIMING ( PCMCIA_SHT(2) \
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| PCMCIA_SST(2) \
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| PCMCIA_SL(4))
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#endif
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#if defined(CONFIG_LWMON) || defined(CONFIG_NSCU)
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#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(9) \
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| PCMCIA_SST(3) \
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| PCMCIA_SL(12))
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#else
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#define CFG_PCMCIA_TIMING ( PCMCIA_SHT(2) \
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| PCMCIA_SST(4) \
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| PCMCIA_SL(9))
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#endif
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/* -------------------------------------------------------------------- */
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int pcmcia_on (void)
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{
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u_long reg, base;
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pcmcia_win_t *win;
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u_int slotbit;
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u_int rc, slot;
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int i;
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debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
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/* intialize the fixed memory windows */
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win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
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base = CFG_PCMCIA_MEM_ADDR;
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if((reg = m8xx_get_graycode(CFG_PCMCIA_MEM_SIZE)) == -1) {
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printf ("Cannot set window size to 0x%08x\n",
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CFG_PCMCIA_MEM_SIZE);
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return (1);
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}
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slotbit = PCMCIA_SLOT_x;
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for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
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win->br = base;
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#if (PCMCIA_SOCKETS_NO == 2)
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if (i == 4) /* Another slot starting from win 4 */
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slotbit = (slotbit ? PCMCIA_PSLOT_A : PCMCIA_PSLOT_B);
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#endif
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switch (i) {
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#ifdef CONFIG_IDE_8xx_PCCARD
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case 4:
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#ifdef CONFIG_HMI10
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{ /* map FRAM area */
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win->or = ( PCMCIA_BSIZE_256K
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| PCMCIA_PPS_8
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| PCMCIA_PRS_ATTR
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| slotbit
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| PCMCIA_PV
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| HMI10_FRAM_TIMING );
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break;
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}
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#endif
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case 0: { /* map attribute memory */
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win->or = ( PCMCIA_BSIZE_64M
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| PCMCIA_PPS_8
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| PCMCIA_PRS_ATTR
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| slotbit
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| PCMCIA_PV
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| CFG_PCMCIA_TIMING );
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break;
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}
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case 5:
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case 1: { /* map I/O window for data reg */
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win->or = ( PCMCIA_BSIZE_1K
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| PCMCIA_PPS_16
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| PCMCIA_PRS_IO
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| slotbit
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| PCMCIA_PV
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| CFG_PCMCIA_TIMING );
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break;
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}
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case 6:
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case 2: { /* map I/O window for cmd/ctrl reg block */
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win->or = ( PCMCIA_BSIZE_1K
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| PCMCIA_PPS_8
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| PCMCIA_PRS_IO
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| slotbit
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| PCMCIA_PV
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| CFG_PCMCIA_TIMING );
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break;
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}
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#endif /* CONFIG_IDE_8xx_PCCARD */
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#ifdef CONFIG_HMI10
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case 3: { /* map I/O window for 4xUART data/ctrl */
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win->br += 0x40000;
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win->or = ( PCMCIA_BSIZE_256K
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| PCMCIA_PPS_8
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| PCMCIA_PRS_IO
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| slotbit
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| PCMCIA_PV
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| CFG_PCMCIA_TIMING );
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break;
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}
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#endif /* CONFIG_HMI10 */
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default: /* set to not valid */
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win->or = 0;
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break;
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}
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debug ("MemWin %d: PBR 0x%08lX POR %08lX\n",
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i, win->br, win->or);
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base += CFG_PCMCIA_MEM_SIZE;
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++win;
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}
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for (i=0, rc=0, slot=_slot_; i<PCMCIA_SOCKETS_NO; i++, slot = !slot) {
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/* turn off voltage */
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if ((rc = pcmcia_voltage_set(slot, 0, 0)))
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continue;
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/* Enable external hardware */
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if ((rc = pcmcia_hardware_enable(slot)))
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continue;
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#ifdef CONFIG_IDE_8xx_PCCARD
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if ((rc = check_ide_device(i)))
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continue;
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#endif
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}
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return rc;
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}
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) || defined(CONFIG_CMD_PCMCIA)
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int pcmcia_off (void)
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{
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int i;
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pcmcia_win_t *win;
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printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
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/* clear interrupt state, and disable interrupts */
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((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pscr = PCMCIA_MASK(_slot_);
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((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_per &= ~PCMCIA_MASK(_slot_);
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/* turn off interrupt and disable CxOE */
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PCMCIA_PGCRX(_slot_) = __MY_PCMCIA_GCRX_CXOE;
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/* turn off memory windows */
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win = (pcmcia_win_t *)(&((immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pbr0);
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for (i=0; i<PCMCIA_MEM_WIN_NO; ++i) {
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/* disable memory window */
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win->or = 0;
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++win;
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}
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/* turn off voltage */
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pcmcia_voltage_set(_slot_, 0, 0);
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/* disable external hardware */
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printf ("Shutdown and Poweroff " PCMCIA_SLOT_MSG "\n");
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pcmcia_hardware_disable(_slot_);
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return 0;
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}
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#endif /* CFG_CMD_PCMCIA */
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static u_int m8xx_get_graycode(u_int size)
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{
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u_int k;
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for (k = 0; k < M8XX_SIZES_NO; k++) {
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if(m8xx_size_to_gray[k] == size)
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break;
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}
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if((k == M8XX_SIZES_NO) || (m8xx_size_to_gray[k] == -1))
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k = -1;
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return k;
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}
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#if 0
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#if defined(CONFIG_RPXCLASSIC) || defined(CONFIG_RPXLITE)
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/* The RPX boards seems to have it's bus monitor timeout set to 6*8 clocks.
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* SYPCR is write once only, therefore must the slowest memory be faster
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* than the bus monitor or we will get a machine check due to the bus timeout.
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*/
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#undef PCMCIA_BMT_LIMIT
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#define PCMCIA_BMT_LIMIT (6*8)
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#endif
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static u_int m8xx_get_speed(u_int ns, u_int is_io)
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{
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u_int reg, clocks, psst, psl, psht;
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if(!ns) {
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/*
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* We get called with IO maps setup to 0ns
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* if not specified by the user.
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* They should be 255ns.
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*/
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if(is_io)
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ns = 255;
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else
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ns = 100; /* fast memory if 0 */
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}
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/*
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* In PSST, PSL, PSHT fields we tell the controller
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* timing parameters in CLKOUT clock cycles.
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* CLKOUT is the same as GCLK2_50.
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*/
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/* how we want to adjust the timing - in percent */
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#define ADJ 180 /* 80 % longer accesstime - to be sure */
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clocks = ((M8XX_BUSFREQ / 1000) * ns) / 1000;
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clocks = (clocks * ADJ) / (100*1000);
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if(clocks >= PCMCIA_BMT_LIMIT) {
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DEBUG(0, "Max access time limit reached\n");
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clocks = PCMCIA_BMT_LIMIT-1;
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}
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psst = clocks / 7; /* setup time */
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psht = clocks / 7; /* hold time */
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psl = (clocks * 5) / 7; /* strobe length */
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psst += clocks - (psst + psht + psl);
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reg = psst << 12;
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reg |= psl << 7;
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reg |= psht << 16;
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return reg;
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}
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#endif /* 0 */
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#endif /* CONFIG_8xx && CONFIG_PCMCIA */
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