upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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193 lines
6.8 KiB
193 lines
6.8 KiB
/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _PCI_PARTS_H_
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#define _PCI_PARTS_H_
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/* Board specific file containing:
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* - PCI Memory Mapping
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* - PCI IO Mapping
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* - PCI Interrupt Mapping
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*/
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/* PIP405 PCI INT Routing:
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* IRQ0 VECTOR
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* PIXX4 IDSEL = AD16 INTA# 28 (Function 2 USB is INTD# = 31)
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* VGA IDSEL = AD17 INTB# 29
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* SCSI IDSEL = AD18 INTC# 30
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* PC104 IDSEL0 = AD20 INTA# 28
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* PC104 IDSEL1 = AD21 INTB# 29
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* PC104 IDSEL2 = AD22 INTC# 30
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* PC104 IDSEL3 = AD23 INTD# 31
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*
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* busdevfunc = EXXX XXXX BBBB BBBB DDDD DFFF RRRR RR00
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* ^ ^ ^ ^ ^
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* 31 23 15 10 7
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* E = Enabled
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* B = Bussnumber
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* D = Devicenumber (Device0 = AD10)
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* F = Functionnumber
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* R = Registernumber
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*
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* Device = (busdevfunc>>11) + 10
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* Vector = devicenumber % 4 + 28
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*
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*/
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#define PCI_HIGHEST_ON_BOARD_ID 19
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/*#define PCI_DEV_NUMBER(x) (((x>>11) & 0x1f) + 10) */
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#define PCI_IRQ_VECTOR(x) ((PCI_DEV(x) + 10) % 4) + 28
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/* PCI Device List for PIP405 */
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/* Mapping:
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* +-------------+------------+------------+--------------------------------+
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* | PCI MemAddr | PCI IOAddr | Local Addr | Device / Function |
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* +-------------+------------+------------+--------------------------------+
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* | 0x00000000 | | 0xA0000000 | ISA Memory (hard wired) |
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* | 0x00FFFFFF | | 0xA0FFFFFF | |
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* +-------------+------------+------------+--------------------------------+
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* | | 0x00000000 | 0xE8000000 | ISA IO (hard wired) |
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* | | 0x0000FFFF | 0xE800FFFF | |
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* +-------------+------------+------------+--------------------------------+
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* | 0x80000000 | | 0x80000000 | VGA Controller Memory |
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* | 0x80FFFFFF | | 0x80FFFFFF | |
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* +-------------+------------+------------+--------------------------------+
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* | 0x81000000 | | 0x81000000 | SCSI Controller Memory |
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* | 0x81FFFFFF | | 0x81FFFFFF | |
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* +-------------+------------+------------+--------------------------------+
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*/
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struct pci_pip405_config_entry {
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int index; /* address */
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unsigned long val; /* value */
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int width; /* data size */
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};
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extern void pci_pip405_write_regs(struct pci_controller *,
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pci_dev_t,
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struct pci_config_table *);
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/* PIIX4 ISA Bridge Function 0 */
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static struct pci_pip405_config_entry piix4_isa_bridge_f0[] = {
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{PCI_CFG_PIIX4_SERIRQ, 0xD0, 1}, /* enable Continous SERIRQ Pin */
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{PCI_CFG_PIIX4_GENCFG, 0x00018041, 4}, /* enable SERIRQs, ISA, PNP, GPI11 */
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{PCI_CFG_PIIX4_TOM, 0xFE, 1}, /* Top of Memory */
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{PCI_CFG_PIIX4_XBCS, 0x02C4, 2}, /* disable all peri CS */
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{PCI_CFG_PIIX4_RTCCFG, 0x21, 1}, /* enable RTC */
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#if defined(CONFIG_PIP405)
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{PCI_CFG_PIIX4_MBDMA, 0x82, 1}, /* set MBDMA0 to DMA 2 */
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{PCI_CFG_PIIX4_MBDMA+1, 0x83, 1}, /* set MBDMA1 to DMA 3 */
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#endif
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{PCI_CFG_PIIX4_DLC, 0x0, 1}, /* disable passive release feature */
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{ } /* end of device table */
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};
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/* PIIX4 IDE Controller Function 1 */
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static struct pci_pip405_config_entry piix4_ide_cntrl_f1[] = {
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{PCI_CFG_PIIX4_BMIBA, 0x0001000, 4}, /* set BMI to a valid address */
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{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
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#if !defined(CONFIG_MIP405T)
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{PCI_CFG_PIIX4_IDETIM, 0x80008000, 4}, /* enable Both IDE channels */
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#else
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{PCI_CFG_PIIX4_IDETIM, 0x00008000, 4}, /* enable IDE channel0 */
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#endif
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{ } /* end of device table */
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};
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/* PIIX4 USB Controller Function 2 */
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static struct pci_pip405_config_entry piix4_usb_cntrl_f2[] = {
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#if !defined(CONFIG_MIP405T)
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{PCI_INTERRUPT_LINE, 31, 1}, /* Int vector = 31 */
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{PCI_BASE_ADDRESS_4, 0x0000E001, 4}, /* Set IO Address to 0xe000 to 0xe01F */
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{PCI_LATENCY_TIMER, 0x80, 1}, /* Latency Timer 0x80 */
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{0xC0, 0x2000, 2}, /* Legacy support */
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{PCI_COMMAND, 0x0005, 2}, /* enable IO access and Master */
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#endif
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{ } /* end of device table */
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};
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/* PIIX4 Power Management Function 3 */
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static struct pci_pip405_config_entry piix4_pmm_cntrl_f3[] = {
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{PCI_CFG_PIIX4_PMBA, 0x00004000, 4}, /* set PMBA to "valid" value */
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{PCI_CFG_PIIX4_SMBBA, 0x00005000, 4}, /* set SMBBA to "valid" value */
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{PCI_CFG_PIIX4_PMMISC, 0x01, 1}, /* enable PMBA IO access */
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{PCI_COMMAND, 0x0001, 2}, /* enable IO access */
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{ } /* end of device table */
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};
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/* PPC405 Dummy only used to prevent autosetup on this host bridge */
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static struct pci_pip405_config_entry ppc405_dummy[] = {
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{ } /* end of device table */
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};
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void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
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struct pci_config_table *entry);
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static struct pci_config_table pci_pip405_config_table[]={
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{PCI_VENDOR_ID_IBM, /* 405 dummy */
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PCI_DEVICE_ID_IBM_405GP,
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PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID, 0,
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pci_pip405_write_regs, {(unsigned long) ppc405_dummy}},
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{PCI_VENDOR_ID_INTEL, /* PIIX4 ISA Bridge Function 0 */
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PCI_DEVICE_ID_INTEL_82371AB_0,
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PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID, 0,
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pci_pip405_write_regs, {(unsigned long) piix4_isa_bridge_f0}},
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{PCI_VENDOR_ID_INTEL, /* PIIX4 IDE Controller Function 1 */
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PCI_DEVICE_ID_INTEL_82371AB,
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PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID, 1,
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pci_pip405_write_regs, {(unsigned long) piix4_ide_cntrl_f1}},
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{PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 2 */
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PCI_DEVICE_ID_INTEL_82371AB_2,
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PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID, 2,
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pci_pip405_write_regs, {(unsigned long) piix4_usb_cntrl_f2}},
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{PCI_VENDOR_ID_INTEL, /* PIIX4 USB Controller Function 3 */
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PCI_DEVICE_ID_INTEL_82371AB_3,
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PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID, 3,
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pci_pip405_write_regs, {(unsigned long) piix4_pmm_cntrl_f3}},
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{PCI_ANY_ID,
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PCI_ANY_ID,
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PCI_CLASS_DISPLAY_VGA,
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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pci_405gp_setup_vga},
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{PCI_ANY_ID,
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PCI_ANY_ID,
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PCI_CLASS_NOT_DEFINED_VGA,
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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pci_405gp_setup_vga},
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{ }
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};
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#endif /* _PCI_PARTS_H_ */
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