upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Peter Tyser d9c147f371 85xx, 86xx: Add common board_add_ram_info() ... Previously, 85xx and 86xx boards would display DRAM information on bootup such as: ... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ... This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner: ... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		16 years ago
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