upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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305 lines
7.0 KiB
305 lines
7.0 KiB
/*
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* Copyright (C) 2011 Ilya Yanok, Emcraft Systems
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*
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* Based on: mach-davinci/emac_defs.h
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DAVINCI_EMAC_H_
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#define _DAVINCI_EMAC_H_
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/* Ethernet Min/Max packet size */
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#define EMAC_MIN_ETHERNET_PKT_SIZE 60
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#define EMAC_MAX_ETHERNET_PKT_SIZE 1518
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/* Buffer size (should be aligned on 32 byte and cache line) */
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#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\
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ARCH_DMA_MINALIGN)
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/* Number of RX packet buffers
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* NOTE: Only 1 buffer supported as of now
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*/
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#define EMAC_MAX_RX_BUFFERS 10
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/***********************************************
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******** Internally used macros ***************
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***********************************************/
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#define EMAC_CH_TX 1
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#define EMAC_CH_RX 0
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/* Each descriptor occupies 4 words, lets start RX desc's at 0 and
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* reserve space for 64 descriptors max
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*/
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#define EMAC_RX_DESC_BASE 0x0
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#define EMAC_TX_DESC_BASE 0x1000
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/* EMAC Teardown value */
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#define EMAC_TEARDOWN_VALUE 0xfffffffc
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/* MII Status Register */
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#define MII_STATUS_REG 1
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/* PHY Configuration register */
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#define PHY_CONF_TXCLKEN (1 << 5)
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/* Number of statistics registers */
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#define EMAC_NUM_STATS 36
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/* EMAC Descriptor */
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typedef volatile struct _emac_desc
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{
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u_int32_t next; /* Pointer to next descriptor
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in chain */
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u_int8_t *buffer; /* Pointer to data buffer */
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u_int32_t buff_off_len; /* Buffer Offset(MSW) and Length(LSW) */
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u_int32_t pkt_flag_len; /* Packet Flags(MSW) and Length(LSW) */
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} emac_desc;
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/* CPPI bit positions */
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#define EMAC_CPPI_SOP_BIT (0x80000000)
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#define EMAC_CPPI_EOP_BIT (0x40000000)
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#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000)
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#define EMAC_CPPI_EOQ_BIT (0x10000000)
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#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000)
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#define EMAC_CPPI_PASS_CRC_BIT (0x04000000)
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#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000)
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#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20)
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#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1)
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#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7)
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#define EMAC_MACCONTROL_GIGFORCE (1 << 17)
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#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15)
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#define EMAC_MAC_ADDR_MATCH (1 << 19)
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#define EMAC_MAC_ADDR_IS_VALID (1 << 20)
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#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
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#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
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#define MDIO_CONTROL_IDLE (0x80000000)
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#define MDIO_CONTROL_ENABLE (0x40000000)
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#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
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#define MDIO_CONTROL_FAULT (0x80000)
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#define MDIO_USERACCESS0_GO (0x80000000)
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#define MDIO_USERACCESS0_WRITE_READ (0x0)
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#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000)
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#define MDIO_USERACCESS0_ACK (0x20000000)
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/* Ethernet MAC Registers Structure */
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typedef struct {
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dv_reg TXIDVER;
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dv_reg TXCONTROL;
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dv_reg TXTEARDOWN;
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u_int8_t RSVD0[4];
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dv_reg RXIDVER;
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dv_reg RXCONTROL;
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dv_reg RXTEARDOWN;
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u_int8_t RSVD1[100];
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dv_reg TXINTSTATRAW;
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dv_reg TXINTSTATMASKED;
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dv_reg TXINTMASKSET;
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dv_reg TXINTMASKCLEAR;
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dv_reg MACINVECTOR;
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u_int8_t RSVD2[12];
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dv_reg RXINTSTATRAW;
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dv_reg RXINTSTATMASKED;
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dv_reg RXINTMASKSET;
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dv_reg RXINTMASKCLEAR;
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dv_reg MACINTSTATRAW;
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dv_reg MACINTSTATMASKED;
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dv_reg MACINTMASKSET;
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dv_reg MACINTMASKCLEAR;
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u_int8_t RSVD3[64];
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dv_reg RXMBPENABLE;
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dv_reg RXUNICASTSET;
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dv_reg RXUNICASTCLEAR;
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dv_reg RXMAXLEN;
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dv_reg RXBUFFEROFFSET;
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dv_reg RXFILTERLOWTHRESH;
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u_int8_t RSVD4[8];
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dv_reg RX0FLOWTHRESH;
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dv_reg RX1FLOWTHRESH;
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dv_reg RX2FLOWTHRESH;
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dv_reg RX3FLOWTHRESH;
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dv_reg RX4FLOWTHRESH;
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dv_reg RX5FLOWTHRESH;
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dv_reg RX6FLOWTHRESH;
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dv_reg RX7FLOWTHRESH;
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dv_reg RX0FREEBUFFER;
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dv_reg RX1FREEBUFFER;
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dv_reg RX2FREEBUFFER;
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dv_reg RX3FREEBUFFER;
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dv_reg RX4FREEBUFFER;
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dv_reg RX5FREEBUFFER;
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dv_reg RX6FREEBUFFER;
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dv_reg RX7FREEBUFFER;
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dv_reg MACCONTROL;
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dv_reg MACSTATUS;
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dv_reg EMCONTROL;
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dv_reg FIFOCONTROL;
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dv_reg MACCONFIG;
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dv_reg SOFTRESET;
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u_int8_t RSVD5[88];
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dv_reg MACSRCADDRLO;
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dv_reg MACSRCADDRHI;
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dv_reg MACHASH1;
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dv_reg MACHASH2;
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dv_reg BOFFTEST;
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dv_reg TPACETEST;
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dv_reg RXPAUSE;
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dv_reg TXPAUSE;
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u_int8_t RSVD6[16];
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dv_reg RXGOODFRAMES;
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dv_reg RXBCASTFRAMES;
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dv_reg RXMCASTFRAMES;
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dv_reg RXPAUSEFRAMES;
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dv_reg RXCRCERRORS;
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dv_reg RXALIGNCODEERRORS;
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dv_reg RXOVERSIZED;
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dv_reg RXJABBER;
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dv_reg RXUNDERSIZED;
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dv_reg RXFRAGMENTS;
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dv_reg RXFILTERED;
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dv_reg RXQOSFILTERED;
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dv_reg RXOCTETS;
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dv_reg TXGOODFRAMES;
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dv_reg TXBCASTFRAMES;
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dv_reg TXMCASTFRAMES;
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dv_reg TXPAUSEFRAMES;
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dv_reg TXDEFERRED;
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dv_reg TXCOLLISION;
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dv_reg TXSINGLECOLL;
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dv_reg TXMULTICOLL;
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dv_reg TXEXCESSIVECOLL;
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dv_reg TXLATECOLL;
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dv_reg TXUNDERRUN;
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dv_reg TXCARRIERSENSE;
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dv_reg TXOCTETS;
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dv_reg FRAME64;
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dv_reg FRAME65T127;
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dv_reg FRAME128T255;
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dv_reg FRAME256T511;
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dv_reg FRAME512T1023;
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dv_reg FRAME1024TUP;
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dv_reg NETOCTETS;
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dv_reg RXSOFOVERRUNS;
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dv_reg RXMOFOVERRUNS;
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dv_reg RXDMAOVERRUNS;
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u_int8_t RSVD7[624];
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dv_reg MACADDRLO;
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dv_reg MACADDRHI;
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dv_reg MACINDEX;
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u_int8_t RSVD8[244];
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dv_reg TX0HDP;
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dv_reg TX1HDP;
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dv_reg TX2HDP;
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dv_reg TX3HDP;
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dv_reg TX4HDP;
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dv_reg TX5HDP;
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dv_reg TX6HDP;
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dv_reg TX7HDP;
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dv_reg RX0HDP;
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dv_reg RX1HDP;
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dv_reg RX2HDP;
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dv_reg RX3HDP;
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dv_reg RX4HDP;
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dv_reg RX5HDP;
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dv_reg RX6HDP;
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dv_reg RX7HDP;
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dv_reg TX0CP;
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dv_reg TX1CP;
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dv_reg TX2CP;
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dv_reg TX3CP;
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dv_reg TX4CP;
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dv_reg TX5CP;
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dv_reg TX6CP;
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dv_reg TX7CP;
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dv_reg RX0CP;
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dv_reg RX1CP;
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dv_reg RX2CP;
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dv_reg RX3CP;
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dv_reg RX4CP;
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dv_reg RX5CP;
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dv_reg RX6CP;
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dv_reg RX7CP;
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} emac_regs;
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/* EMAC Wrapper Registers Structure */
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typedef struct {
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#ifdef DAVINCI_EMAC_VERSION2
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dv_reg idver;
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dv_reg softrst;
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dv_reg emctrl;
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dv_reg c0rxthreshen;
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dv_reg c0rxen;
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dv_reg c0txen;
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dv_reg c0miscen;
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dv_reg c1rxthreshen;
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dv_reg c1rxen;
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dv_reg c1txen;
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dv_reg c1miscen;
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dv_reg c2rxthreshen;
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dv_reg c2rxen;
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dv_reg c2txen;
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dv_reg c2miscen;
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dv_reg c0rxthreshstat;
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dv_reg c0rxstat;
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dv_reg c0txstat;
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dv_reg c0miscstat;
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dv_reg c1rxthreshstat;
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dv_reg c1rxstat;
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dv_reg c1txstat;
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dv_reg c1miscstat;
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dv_reg c2rxthreshstat;
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dv_reg c2rxstat;
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dv_reg c2txstat;
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dv_reg c2miscstat;
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dv_reg c0rximax;
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dv_reg c0tximax;
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dv_reg c1rximax;
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dv_reg c1tximax;
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dv_reg c2rximax;
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dv_reg c2tximax;
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#else
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u_int8_t RSVD0[4100];
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dv_reg EWCTL;
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dv_reg EWINTTCNT;
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#endif
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} ewrap_regs;
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/* EMAC MDIO Registers Structure */
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typedef struct {
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dv_reg VERSION;
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dv_reg CONTROL;
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dv_reg ALIVE;
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dv_reg LINK;
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dv_reg LINKINTRAW;
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dv_reg LINKINTMASKED;
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u_int8_t RSVD0[8];
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dv_reg USERINTRAW;
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dv_reg USERINTMASKED;
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dv_reg USERINTMASKSET;
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dv_reg USERINTMASKCLEAR;
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u_int8_t RSVD1[80];
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dv_reg USERACCESS0;
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dv_reg USERPHYSEL0;
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dv_reg USERACCESS1;
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dv_reg USERPHYSEL1;
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} mdio_regs;
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int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
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int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
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typedef struct {
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char name[64];
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int (*init)(int phy_addr);
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int (*is_phy_connected)(int phy_addr);
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int (*get_link_speed)(int phy_addr);
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int (*auto_negotiate)(int phy_addr);
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} phy_t;
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#endif /* _DAVINCI_EMAC_H_ */
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