upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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501 lines
13 KiB
501 lines
13 KiB
#ifndef __DMC_H__
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#define __DMC_H__
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#ifndef __ASSEMBLY__
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struct exynos4_dmc {
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unsigned int concontrol;
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unsigned int memcontrol;
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unsigned int memconfig0;
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unsigned int memconfig1;
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unsigned int directcmd;
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unsigned int prechconfig;
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unsigned int phycontrol0;
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unsigned int phycontrol1;
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unsigned int phycontrol2;
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unsigned int phycontrol3;
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unsigned int pwrdnconfig;
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unsigned char res1[0x4];
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unsigned int timingref;
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unsigned int timingrow;
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unsigned int timingdata;
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unsigned int timingpower;
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unsigned int phystatus;
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unsigned int phyzqcontrol;
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unsigned int chip0status;
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unsigned int chip1status;
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unsigned int arefstatus;
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unsigned int mrstatus;
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unsigned int phytest0;
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unsigned int phytest1;
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unsigned int qoscontrol0;
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unsigned int qosconfig0;
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unsigned int qoscontrol1;
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unsigned int qosconfig1;
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unsigned int qoscontrol2;
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unsigned int qosconfig2;
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unsigned int qoscontrol3;
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unsigned int qosconfig3;
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unsigned int qoscontrol4;
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unsigned int qosconfig4;
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unsigned int qoscontrol5;
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unsigned int qosconfig5;
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unsigned int qoscontrol6;
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unsigned int qosconfig6;
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unsigned int qoscontrol7;
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unsigned int qosconfig7;
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unsigned int qoscontrol8;
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unsigned int qosconfig8;
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unsigned int qoscontrol9;
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unsigned int qosconfig9;
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unsigned int qoscontrol10;
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unsigned int qosconfig10;
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unsigned int qoscontrol11;
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unsigned int qosconfig11;
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unsigned int qoscontrol12;
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unsigned int qosconfig12;
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unsigned int qoscontrol13;
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unsigned int qosconfig13;
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unsigned int qoscontrol14;
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unsigned int qosconfig14;
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unsigned int qoscontrol15;
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unsigned int qosconfig15;
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unsigned int qostimeout0;
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unsigned int qostimeout1;
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unsigned char res2[0x8];
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unsigned int ivcontrol;
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unsigned char res3[0x8];
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unsigned int perevconfig;
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unsigned char res4[0xDF00];
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unsigned int pmnc_ppc_a;
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unsigned char res5[0xC];
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unsigned int cntens_ppc_a;
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unsigned char res6[0xC];
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unsigned int cntenc_ppc_a;
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unsigned char res7[0xC];
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unsigned int intens_ppc_a;
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unsigned char res8[0xC];
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unsigned int intenc_ppc_a;
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unsigned char res9[0xC];
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unsigned int flag_ppc_a;
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unsigned char res10[0xAC];
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unsigned int ccnt_ppc_a;
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unsigned char res11[0xC];
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unsigned int pmcnt0_ppc_a;
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unsigned char res12[0xC];
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unsigned int pmcnt1_ppc_a;
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unsigned char res13[0xC];
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unsigned int pmcnt2_ppc_a;
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unsigned char res14[0xC];
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unsigned int pmcnt3_ppc_a;
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unsigned char res15[0xEBC];
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unsigned int pmnc_ppc_m;
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unsigned char res16[0xC];
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unsigned int cntens_ppc_m;
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unsigned char res17[0xC];
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unsigned int cntenc_ppc_m;
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unsigned char res18[0xC];
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unsigned int intens_ppc_m;
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unsigned char res19[0xC];
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unsigned int intenc_ppc_m;
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unsigned char res20[0xC];
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unsigned int flag_ppc_m;
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unsigned char res21[0xAC];
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unsigned int ccnt_ppc_m;
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unsigned char res22[0xC];
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unsigned int pmcnt0_ppc_m;
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unsigned char res23[0xC];
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unsigned int pmcnt1_ppc_m;
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unsigned char res24[0xC];
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unsigned int pmcnt2_ppc_m;
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unsigned char res25[0xC];
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unsigned int pmcnt3_ppc_m;
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};
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struct exynos5_dmc {
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unsigned int concontrol;
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unsigned int memcontrol;
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unsigned int memconfig0;
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unsigned int memconfig1;
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unsigned int directcmd;
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unsigned int prechconfig;
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unsigned int phycontrol0;
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unsigned char res1[0xc];
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unsigned int pwrdnconfig;
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unsigned int timingpzq;
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unsigned int timingref;
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unsigned int timingrow;
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unsigned int timingdata;
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unsigned int timingpower;
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unsigned int phystatus;
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unsigned char res2[0x4];
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unsigned int chipstatus_ch0;
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unsigned int chipstatus_ch1;
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unsigned char res3[0x4];
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unsigned int mrstatus;
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unsigned char res4[0x8];
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unsigned int qoscontrol0;
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unsigned char resr5[0x4];
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unsigned int qoscontrol1;
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unsigned char res6[0x4];
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unsigned int qoscontrol2;
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unsigned char res7[0x4];
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unsigned int qoscontrol3;
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unsigned char res8[0x4];
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unsigned int qoscontrol4;
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unsigned char res9[0x4];
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unsigned int qoscontrol5;
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unsigned char res10[0x4];
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unsigned int qoscontrol6;
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unsigned char res11[0x4];
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unsigned int qoscontrol7;
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unsigned char res12[0x4];
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unsigned int qoscontrol8;
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unsigned char res13[0x4];
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unsigned int qoscontrol9;
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unsigned char res14[0x4];
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unsigned int qoscontrol10;
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unsigned char res15[0x4];
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unsigned int qoscontrol11;
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unsigned char res16[0x4];
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unsigned int qoscontrol12;
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unsigned char res17[0x4];
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unsigned int qoscontrol13;
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unsigned char res18[0x4];
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unsigned int qoscontrol14;
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unsigned char res19[0x4];
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unsigned int qoscontrol15;
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unsigned char res20[0x14];
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unsigned int ivcontrol;
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unsigned int wrtra_config;
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unsigned int rdlvl_config;
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unsigned char res21[0x8];
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unsigned int brbrsvconfig;
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unsigned int brbqosconfig;
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unsigned int membaseconfig0;
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unsigned int membaseconfig1;
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unsigned char res22[0xc];
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unsigned int wrlvl_config;
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unsigned char res23[0xc];
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unsigned int perevcontrol;
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unsigned int perev0config;
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unsigned int perev1config;
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unsigned int perev2config;
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unsigned int perev3config;
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unsigned char res24[0xdebc];
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unsigned int pmnc_ppc_a;
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unsigned char res25[0xc];
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unsigned int cntens_ppc_a;
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unsigned char res26[0xc];
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unsigned int cntenc_ppc_a;
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unsigned char res27[0xc];
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unsigned int intens_ppc_a;
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unsigned char res28[0xc];
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unsigned int intenc_ppc_a;
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unsigned char res29[0xc];
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unsigned int flag_ppc_a;
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unsigned char res30[0xac];
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unsigned int ccnt_ppc_a;
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unsigned char res31[0xc];
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unsigned int pmcnt0_ppc_a;
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unsigned char res32[0xc];
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unsigned int pmcnt1_ppc_a;
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unsigned char res33[0xc];
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unsigned int pmcnt2_ppc_a;
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unsigned char res34[0xc];
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unsigned int pmcnt3_ppc_a;
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};
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struct exynos5420_dmc {
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unsigned int concontrol;
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unsigned int memcontrol;
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unsigned int cgcontrol;
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unsigned char res500[0x4];
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unsigned int directcmd;
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unsigned int prechconfig0;
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unsigned int phycontrol0;
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unsigned int prechconfig1;
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unsigned char res1[0x8];
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unsigned int pwrdnconfig;
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unsigned int timingpzq;
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unsigned int timingref;
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unsigned int timingrow0;
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unsigned int timingdata0;
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unsigned int timingpower0;
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unsigned int phystatus;
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unsigned int etctiming;
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unsigned int chipstatus;
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unsigned char res3[0x8];
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unsigned int mrstatus;
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unsigned char res4[0x8];
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unsigned int qoscontrol0;
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unsigned char resr5[0x4];
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unsigned int qoscontrol1;
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unsigned char res6[0x4];
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unsigned int qoscontrol2;
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unsigned char res7[0x4];
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unsigned int qoscontrol3;
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unsigned char res8[0x4];
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unsigned int qoscontrol4;
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unsigned char res9[0x4];
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unsigned int qoscontrol5;
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unsigned char res10[0x4];
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unsigned int qoscontrol6;
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unsigned char res11[0x4];
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unsigned int qoscontrol7;
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unsigned char res12[0x4];
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unsigned int qoscontrol8;
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unsigned char res13[0x4];
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unsigned int qoscontrol9;
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unsigned char res14[0x4];
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unsigned int qoscontrol10;
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unsigned char res15[0x4];
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unsigned int qoscontrol11;
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unsigned char res16[0x4];
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unsigned int qoscontrol12;
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unsigned char res17[0x4];
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unsigned int qoscontrol13;
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unsigned char res18[0x4];
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unsigned int qoscontrol14;
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unsigned char res19[0x4];
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unsigned int qoscontrol15;
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unsigned char res20[0x4];
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unsigned int timing_set_sw;
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unsigned int timingrow1;
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unsigned int timingdata1;
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unsigned int timingpower1;
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unsigned char res300[0x4];
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unsigned int wrtra_config;
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unsigned int rdlvl_config;
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unsigned char res21[0x4];
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unsigned int brbrsvcontrol;
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unsigned int brbrsvconfig;
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unsigned int brbqosconfig;
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unsigned char res301[0x14];
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unsigned int wrlvl_config0;
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unsigned int wrlvl_config1;
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unsigned int wrlvl_status;
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unsigned char res23[0x4];
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unsigned int ppcclockon;
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unsigned int perevconfig0;
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unsigned int perevconfig1;
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unsigned int perevconfig2;
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unsigned int perevconfig3;
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unsigned char res24[0xc];
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unsigned int control_io_rdata;
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unsigned char res240[0xc];
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unsigned int cacal_config0;
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unsigned int cacal_config1;
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unsigned int cacal_status;
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unsigned char res302[0xa4];
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unsigned int bp_control0;
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unsigned int bp_config0_r;
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unsigned int bp_config0_w;
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unsigned char res303[0x4];
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unsigned int bp_control1;
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unsigned int bp_config1_r;
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unsigned int bp_config1_w;
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unsigned char res304[0x4];
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unsigned int bp_control2;
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unsigned int bp_config2_r;
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unsigned int bp_config2_w;
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unsigned char res305[0x4];
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unsigned int bp_control3;
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unsigned int bp_config3_r;
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unsigned int bp_config3_w;
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unsigned char res306[0xddb4];
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unsigned int pmnc_ppc;
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unsigned char res25[0xc];
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unsigned int cntens_ppc;
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unsigned char res26[0xc];
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unsigned int cntenc_ppc;
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unsigned char res27[0xc];
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unsigned int intens_ppc;
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unsigned char res28[0xc];
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unsigned int intenc_ppc;
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unsigned char res29[0xc];
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unsigned int flag_ppc;
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unsigned char res30[0xac];
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unsigned int ccnt_ppc;
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unsigned char res31[0xc];
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unsigned int pmcnt0_ppc;
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unsigned char res32[0xc];
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unsigned int pmcnt1_ppc;
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unsigned char res33[0xc];
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unsigned int pmcnt2_ppc;
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unsigned char res34[0xc];
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unsigned int pmcnt3_ppc;
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};
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struct exynos5_phy_control {
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unsigned int phy_con0;
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unsigned int phy_con1;
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unsigned int phy_con2;
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unsigned int phy_con3;
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unsigned int phy_con4;
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unsigned char res1[4];
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unsigned int phy_con6;
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unsigned char res2[4];
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unsigned int phy_con8;
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unsigned int phy_con9;
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unsigned int phy_con10;
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unsigned char res3[4];
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unsigned int phy_con12;
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unsigned int phy_con13;
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unsigned int phy_con14;
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unsigned int phy_con15;
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unsigned int phy_con16;
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unsigned char res4[4];
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unsigned int phy_con17;
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unsigned int phy_con18;
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unsigned int phy_con19;
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unsigned int phy_con20;
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unsigned int phy_con21;
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unsigned int phy_con22;
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unsigned int phy_con23;
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unsigned int phy_con24;
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unsigned int phy_con25;
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unsigned int phy_con26;
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unsigned int phy_con27;
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unsigned int phy_con28;
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unsigned int phy_con29;
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unsigned int phy_con30;
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unsigned int phy_con31;
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unsigned int phy_con32;
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unsigned int phy_con33;
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unsigned int phy_con34;
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unsigned int phy_con35;
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unsigned int phy_con36;
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unsigned int phy_con37;
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unsigned int phy_con38;
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unsigned int phy_con39;
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unsigned int phy_con40;
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unsigned int phy_con41;
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unsigned int phy_con42;
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};
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struct exynos5420_phy_control {
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unsigned int phy_con0;
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unsigned int phy_con1;
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unsigned int phy_con2;
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unsigned int phy_con3;
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unsigned int phy_con4;
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unsigned int phy_con5;
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unsigned int phy_con6;
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unsigned char res2[0x4];
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unsigned int phy_con8;
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unsigned char res5[0x4];
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unsigned int phy_con10;
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unsigned int phy_con11;
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unsigned int phy_con12;
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unsigned int phy_con13;
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unsigned int phy_con14;
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unsigned int phy_con15;
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unsigned int phy_con16;
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unsigned char res4[0x4];
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unsigned int phy_con17;
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unsigned int phy_con18;
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unsigned int phy_con19;
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unsigned int phy_con20;
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unsigned int phy_con21;
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unsigned int phy_con22;
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unsigned int phy_con23;
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unsigned int phy_con24;
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unsigned int phy_con25;
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unsigned int phy_con26;
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unsigned int phy_con27;
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unsigned int phy_con28;
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unsigned int phy_con29;
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unsigned int phy_con30;
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unsigned int phy_con31;
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unsigned int phy_con32;
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unsigned int phy_con33;
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unsigned int phy_con34;
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unsigned char res6[0x8];
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unsigned int phy_con37;
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unsigned char res7[0x4];
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unsigned int phy_con39;
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unsigned int phy_con40;
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unsigned int phy_con41;
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unsigned int phy_con42;
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};
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struct exynos5420_tzasc {
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unsigned char res1[0xf00];
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unsigned int membaseconfig0;
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unsigned int membaseconfig1;
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unsigned char res2[0x8];
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unsigned int memconfig0;
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unsigned int memconfig1;
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};
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enum ddr_mode {
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DDR_MODE_DDR2,
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DDR_MODE_DDR3,
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DDR_MODE_LPDDR2,
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DDR_MODE_LPDDR3,
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DDR_MODE_COUNT,
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};
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enum mem_manuf {
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MEM_MANUF_AUTODETECT,
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MEM_MANUF_ELPIDA,
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MEM_MANUF_SAMSUNG,
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MEM_MANUF_COUNT,
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};
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/* CONCONTROL register fields */
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#define CONCONTROL_DFI_INIT_START_SHIFT 28
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#define CONCONTROL_RD_FETCH_SHIFT 12
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#define CONCONTROL_RD_FETCH_MASK (0x7 << CONCONTROL_RD_FETCH_SHIFT)
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#define CONCONTROL_AREF_EN_SHIFT 5
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#define CONCONTROL_UPDATE_MODE (1 << 3)
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/* PRECHCONFIG register field */
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#define PRECHCONFIG_TP_CNT_SHIFT 24
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/* PWRDNCONFIG register field */
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#define PWRDNCONFIG_DPWRDN_CYC_SHIFT 0
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#define PWRDNCONFIG_DSREF_CYC_SHIFT 16
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/* PHY_CON0 register fields */
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#define PHY_CON0_T_WRRDCMD_SHIFT 17
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#define PHY_CON0_T_WRRDCMD_MASK (0x7 << PHY_CON0_T_WRRDCMD_SHIFT)
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#define PHY_CON0_CTRL_DDR_MODE_SHIFT 11
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#define PHY_CON0_CTRL_DDR_MODE_MASK 0x3
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/* PHY_CON1 register fields */
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#define PHY_CON1_RDLVL_RDDATA_ADJ_SHIFT 0
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/* PHY_CON4 rgister fields */
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#define PHY_CON10_CTRL_OFFSETR3 (1 << 24)
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/* PHY_CON12 register fields */
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#define PHY_CON12_CTRL_START_POINT_SHIFT 24
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#define PHY_CON12_CTRL_INC_SHIFT 16
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#define PHY_CON12_CTRL_FORCE_SHIFT 8
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#define PHY_CON12_CTRL_START_SHIFT 6
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#define PHY_CON12_CTRL_START_MASK (1 << PHY_CON12_CTRL_START_SHIFT)
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#define PHY_CON12_CTRL_DLL_ON_SHIFT 5
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#define PHY_CON12_CTRL_DLL_ON_MASK (1 << PHY_CON12_CTRL_DLL_ON_SHIFT)
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#define PHY_CON12_CTRL_REF_SHIFT 1
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/* PHY_CON16 register fields */
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#define PHY_CON16_ZQ_MODE_DDS_SHIFT 24
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#define PHY_CON16_ZQ_MODE_DDS_MASK (0x7 << PHY_CON16_ZQ_MODE_DDS_SHIFT)
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#define PHY_CON16_ZQ_MODE_TERM_SHIFT 21
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#define PHY_CON16_ZQ_MODE_TERM_MASK (0x7 << PHY_CON16_ZQ_MODE_TERM_SHIFT)
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#define PHY_CON16_ZQ_MODE_NOTERM_MASK (1 << 19)
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/* PHY_CON42 register fields */
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#define PHY_CON42_CTRL_BSTLEN_SHIFT 8
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#define PHY_CON42_CTRL_BSTLEN_MASK (0xff << PHY_CON42_CTRL_BSTLEN_SHIFT)
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#define PHY_CON42_CTRL_RDLAT_SHIFT 0
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#define PHY_CON42_CTRL_RDLAT_MASK (0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
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#endif
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#endif
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